PORTS.A

PORTS LIST Release 61 Last change 16jul00
Copyright (c) 1989-1999,2000 Ralf Brown

[This file originally by Wim Osterholt ,
 though it has grown considerably since.]

		XT, AT and PS/2	 I/O port addresses

Do NOT consider this information to be complete and accurate.  If you want
to do hardware programming ALWAYS check the appropriate data sheets (but
even they are sometimes in error!).  Be aware that erroneous port programming
can put your data or even your hardware at risk.

There are a number of memory-mapped addresses in use for I/O; see MEMORY.LST
for details on memory-mapped I/O.

Table of Contents: by Order by Category

Table of Contents by Category

! - document info
- - uncategorized
K - keyboard enhancers
X - expansion bus BIOSes
h - vendor-specific hardware,
p - power management,

! - document info

Note - Note: the port description format is:
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- - uncategorized

Note - Note: the port description format is:

Note: the port description format is:

PPPPw RW  description

where:	PPPP	is the four-digit hex port number or a plus sign and three hex
		digits to indicate an offset from a base port address
	w	is blank for byte-size port, 'w' for word, and 'd' for dword
	R	is dash (or blank) if not readable, 'r' if sometimes readable,
		'R' if "always" readable, '?' if readability unknown
	W	is dash (or blank) if not writable, 'w' if sometimes writable,
		'W' if "always" writable, 'C' if write-clear, and
		'?' if writability unknown

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P0000001F - PORT 0000-001F - DMA 1 - FIRST DIRECT MEMORY ACCESS CONTROLLER (8237)

PORT 0000-001F - DMA 1 - FIRST DIRECT MEMORY ACCESS CONTROLLER (8237)
SeeAlso: PORT 0080h-008Fh"DMA",PORT 00C0h-00DFh

0000  R-  DMA channel 0	current address		byte  0, then byte 1
0000  -W  DMA channel 0	base address		byte  0, then byte 1
0001  RW  DMA channel 0 word count		byte 0, then byte 1
0002  R-  DMA channel 1	current address		byte  0, then byte 1
0002  -W  DMA channel 1	base address		byte  0, then byte 1
0003  RW  DMA channel 1 word count		byte 0, then byte 1
0004  R-  DMA channel 2	current address		byte  0, then byte 1
0004  -W  DMA channel 2	base address		byte  0, then byte 1
0005  RW  DMA channel 2 word count		byte 0, then byte 1
0006  R-  DMA channel 3	current address		byte  0, then byte 1
0006  -W  DMA channel 3	base address		byte  0, then byte 1
0007  RW  DMA channel 3 word count		byte 0, then byte 1

0008  R-  DMA channel 0-3 status register (see #P0001)
0008  -W  DMA channel 0-3 command register (see #P0002)
0009  -W  DMA channel 0-3 write request register (see #P0003)
000A  RW  DMA channel 0-3 mask register (see #P0004)
000B  -W  DMA channel 0-3 mode register (see #P0005)

000C  -W  DMA channel 0-3 clear byte pointer flip-flop register
	  any write clears LSB/MSB flip-flop of address and counter registers
000D  R-  DMA channel 0-3 temporary register
000D  -W  DMA channel 0-3 master clear register
	  any write causes reset of 8237
000E  -W  DMA channel 0-3 clear mask register
	  any write clears masks for all channels
000F  rW  DMA channel 0-3 write mask register (see #P0006)
Notes:	the temporary register is used as holding register in memory-to-memory
	  DMA transfers; it holds the last transferred byte
	channel 2 is used by the floppy disk controller
	on the IBM PC/XT channel 0 was used for the memory refresh and
	  channel 3 was used by the hard disk controller
	on AT and later machines with two DMA controllers, channel 4 is used
	  as a cascade for channels 0-3
	command and request registers do not exist on a PS/2 DMA controller

Bitfields for DMA channel 0-3 status register:
Bit(s)	Description	(Table P0001)
 7	channel 3 request active
 6	channel 2 request active
 5	channel 1 request active
 4	channel 0 request active
 3	channel terminal count on channel 3
 2	channel terminal count on channel 2
 1	channel terminal count on channel 1
 0	channel terminal count on channel 0
SeeAlso: #P0002,#P0481

Bitfields for DMA channel 0-3 command register:
Bit(s)	Description	(Table P0002)
 7	DACK sense active high
 6	DREQ sense active high
 5	=1 extended write selection
	=0 late write selection
 4	rotating priority instead of fixed priority
 3	compressed timing (two clocks instead of four per transfer)
	=1 normal timing (default)
	=0 compressed timing
 2	=1 enable controller
	=0 enable memory-to-memory
 1-0	channel number
SeeAlso: #P0001,#P0004,#P0005,#P0482

Bitfields for DMA channel 0-3 request register:
Bit(s)	Description	(Table P0003)
 7-3	reserved (0)
 2	=0 clear request bit
	=1 set request bit
 1-0	channel number
	00 channel 0 select
	01 channel 1 select
	10 channel 2 select
	11 channel 3 select
SeeAlso: #P0004

Bitfields for DMA channel 0-3 mask register:
Bit(s)	Description	(Table P0004)
 7-3	reserved (0)
 2	=0 clear mask bit
	=1 set mask bit
 1-0	channel number
	00 channel 0 select
	01 channel 1 select
	10 channel 2 select
	11 channel 3 select
SeeAlso: #P0001,#P0002,#P0003,#P0484

Bitfields for DMA channel 0-3 mode register:
Bit(s)	Description	(Table P0005)
 7-6	transfer mode
	00 demand mode
	01 single mode
	10 block mode
	11 cascade mode
 5	direction
	=0 increment address after each transfer
	=1 decrement address
 3-2	operation
	00 verify operation
	01 write to memory
	10 read from memory
	11 reserved
 1-0	channel number
	00 channel 0 select
	01 channel 1 select
	10 channel 2 select
	11 channel 3 select
SeeAlso: #P0002,#P0485

Bitfields for DMA channel 0-3 write mask register:
Bit(s)	Description	(Table P0006)
 7-4	reserved
 3	channel 3 mask bit
 2	channel 2 mask bit
 1	channel 1 mask bit
 0	channel 0 mask bit
Note:	each mask bit is automatically set when the corresponding channel
	  reaches terminal count or an extenal EOP sigmal is received
SeeAlso: #P0004,#P0486

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P0010001F - PORT 0010-001F - DMA CONTROLLER (8237) ON PS/2 MODEL 60 & 80

PORT 0010-001F - DMA CONTROLLER (8237) ON PS/2 MODEL 60 & 80
SeeAlso: PORT 0000h-001Fh,PORT 0080h-008Fh"DMA",PORT 00C0h-00DFh

0018  -W  extended function register (see #P0007)
001A  -W  extended function execute register

Bitfields for DMA extended function register:
Bit(s)	Description	(Table P0007)
 7-4	function code (see #P0008)
 3	reserved (0)
 2-0	channel number
	000 channel 0 select
	001 channel 1 select
	010 channel 2 select
	011 channel 3 select
	100 channel 4 select
	101 channel 5 select
	110 channel 6 select
	111 channel 7 select

(Table P0008)
Values for DMA extended function codes (data go to/from PORT 001Ah):
Value	Description		  Parameters  Results
 00h	current address register      -	      CA0,CA1
 02h	write address		      -	      A0,A1,P
 03h	read  address		   A0,A1,P	 -
 04h	write word count register   C0,C1	 -
 05h	read  word count register     -	       C0,C1
 06h	read status register	      -		 S
 07h	mode register		      -		 M
 09h	mask channel		      -		 -
 0Ah	unmask channel		      -		 -
 0Dh	master clear		      -		 -
Note:	CA0/CA1	  LSB/MSB of the current address register
	A0/A1	  LSB/MSB of the base address register
	P	  DMA page address
	C0/C1	  LSB/MSB of the word count register
	S	  status register value (see #P0001, #P0481)
	M	  mode register value (see #P0005, #P0485)
	first, the extended function register is written, then the extended
	  function register execute register is read/written if the function
	  being executing requires

Bitfields for DMA extended mode register:
Bit(s)	Description	(Table P0009)
 7	reserved (0)
 6	=0 8-bit transfer
	=1 16-bit transfer
 5-4	reserved (0)
 3	transfer type
	=0 read from memory
	=1 write to memory
 2	=0 disable memory write
	=1 enable  memory write
 1	reserved (0)
 0	address select
	=0 use 0 as base address
	=1 use a value from base address register
Note:	the IBM PS/2 model 80 technical reference doesn't seem to mention this
	  register's address

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P0020003F - PORT 0020-003F - PIC 1 - PROGRAMMABLE INTERRUPT CONTROLLER (8259A)

PORT 0020-003F - PIC 1 - PROGRAMMABLE INTERRUPT CONTROLLER (8259A)
SeeAlso: PORT 00A0h-00AFh"PIC 2",INT 08"IRQ0",INT 0F"IRQ7"

0020  -W  PIC initialization command word ICW1 (see #P0010)
0020  -W  PIC output control word OCW2 (see #P0015)
0020  -W  PIC output control word OCW3 (see #P0016)
0020  R-  PIC  interrupt request/in-service registers after OCW3
		request register:
		 bit 7-0 = 0  no active request for the corresponding int. line
			 = 1  active request for corresponding interrupt line
		in-service register:
		 bit 7-0 = 0  corresponding line not currently being serviced
			 = 1  corresponding int. line currently being serviced

0021  -W  PIC ICW2,ICW3,ICW4 immed after ICW1 to 0020 (see #P0011,#P0012,#P0013)
0021  RW  PIC master interrupt mask register OCW1 (see #P0014)

Bitfields for PIC initialization command word ICW1:
Bit(s)	Description	(Table P0010)
 7-5	0 (only used in 8080/8085 mode)
 4	ICW1 is being issued
 3	(LTIM)
	=0  edge triggered mode
	=1  level triggered mode
 2	interrupt vector size
	=0 successive interrupt vectors use 8 bytes (8080/8085)
	=1 successive interrupt vectors use 4 bytes (80x86)
 1	(SNGL)
	=0  cascade mode
	=1  single mode, no ICW3 needed
 0	ICW4 needed
SeeAlso: #P0011,#P0012,#P0013

Bitfields for PIC initialization command word ICW2:
Bit(s)	Description	(Table P0011)
 7-3	address lines A0-A3 of base vector address for PIC
 2-0	reserved
SeeAlso: #P0010,#P0012,#P0013

Bitfields for PIC initialization command word ICW3:
Bit(s)	Description	(Table P0012)
 7-0	=0 slave controller not attached to corresponding interrupt pin
	=1 slave controller attached to corresponding interrupt pin
SeeAlso: #P0010,#P0011,#P0013

Bitfields for PIC initialization command word ICW4:
Bit(s)	Description	(Table P0013)
 7-5	reserved (0)
 4	running in special fully-nested mode
 3-2	mode
	0x nonbuffered mode
	10 buffered mode/slave
	11 buffered mode/master
 1	Auto EOI
 0	=0  8085 mode
	=1  8086/8088 mode
SeeAlso: #P0010,#P0011,#P0012

Bitfields for PIC output control word OCW1:
Bit(s)	Description	(Table P0014)
 7	disable IRQ7 (parallel printer interrupt)
 6	disable IRQ6 (diskette interrupt)
 5	disable IRQ5 (fixed disk interrupt)
 4	disable IRQ4 (serial port 1 interrupt)
 3	disable IRQ3 (serial port 2 interrupt)
 2	disable IRQ2 (video interrupt)
 1	disable IRQ1 (keyboard, mouse, RTC interrupt)
 0	disable IRQ0 (timer interrupt)
SeeAlso: #P0015,#P0016,#P0418

Bitfields for PIC output control word OCW2:
Bit(s)	Description	(Table P0015)
 7-5	operation
	000 rotate in auto EOI mode (clear)
	001 (WORD_A) nonspecific EOI
	010 (WORD_H) no operation
	011 (WORD_B) specific EOI
	100 (WORD_F) rotate in auto EOI mode (set)
	101 (WORD_C) rotate on nonspecific EOI command
	110 (WORD_E) set priority command
	111 (WORD_D) rotate on specific EOI command
 4-3	reserved (00 - signals OCW2)
 2-0	interrupt request to which the command applies
	(only used by WORD_B, WORD_D, and WORD_E)
SeeAlso: #P0014,#P0016

Bitfields for PIC output control word OCW3:
Bit(s)	Description	(Table P0016)
 7	reserved (0)
 6-5	special mask
	0x  no operation
	10  reset special mask
	11  set special mask mode
 4-3	reserved (01 - signals OCW3)
 2	poll command
 1-0	function
	0x  no operation
	10  read interrupt request register on next read from PORT 0020h
	11  read interrupt in-service register on next read from PORT 0020h
Note:	the special mask mode permits all other interrupts (even those with
	  lower priority) to be processed while an interrupt is already in
	  service, but will not re-issue an interrupt for a particular IRQ
	  while it remains in service
SeeAlso: #P0014,#P0015

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P0022 - PORT 0022 - Intel 82439TX Chipset - Power Control register

PORT 0022 - Intel 82439TX Chipset - Power Control register
SeeAlso: PORT 0022h"82443BX"

0022  RW  PM2 Register Block
	bits 7-1: reserved
	bit 0:	Arbiter Disable

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P0022 - PORT 0022 - Intel 82443BX - "PM2_CTL" ACPI Power Control 2 Register

PORT 0022 - Intel 82443BX - "PM2_CTL" ACPI Power Control 2 Register
SeeAlso: PORT 0022h"82439TX",#01142 at INT 1A/AX=B10Ah/SF=8086h

0022  RW  ACPI Power Control Register 2
	bits 7-1: reserved
	bit 0:	disable primary PCI and AGP arbiter requests

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P00220023 - PORT 0022-0023 - CHIP SET DATA

PORT 0022-0023 - CHIP SET DATA
Note:	These two ports are used by numerous chipsets.	Various chipsets are
	  detailed below.

0022  -W  index for accesses to data port
0023  RW  chip set data

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P00220023 - PORT 0022-0023 - Cyrix Cx486SLC/DLC PROCESSOR - CACHE CONFIGURATION REGISTERS

PORT 0022-0023 - Cyrix Cx486SLC/DLC PROCESSOR - CACHE CONFIGURATION REGISTERS
SeeAlso: PORT 0022h"5x86",PORT 0022h"6x86"

0022  -W  index for accesses to next port (see #P0017)
0023  RW  cache configuration register array (indexed by PORT 0022h)
	Note:	the index must be written to PORT 0022h before every access
		  to PORT 0023h; out-of-sequence accesses or index values
		  not supported by the processor generate external I/O cycles

(Table P0017)
Values for Cyrix Cx486SLC/DLC Cache Configuration register number:
 C0h	CR0 (see #P0019)
 C1h	CR1 (see #P0020)
 C4h	non-cacheable region 1, start address bits 31-24
 C5h	non-cacheable region 1, start address bits 23-16
 C6h	non-cacheable region 1, start addr 15-12, size (low nibble) (see #P0018)
 C7h	non-cacheable region 2, start address bits 31-24
 C8h	non-cacheable region 2, start address bits 23-16
 C9h	non-cacheable region 2, start addr 15-12, size (low nibble) (see #P0018)
 CAh	non-cacheable region 3, start address bits 31-24
 CBh	non-cacheable region 3, start address bits 23-16
 CCh	non-cacheable region 3, start addr 15-12, size (low nibble) (see #P0018)
 CDh	non-cacheable region 4, start address bits 31-24
 CEh	non-cacheable region 4, start address bits 23-16
 CFh	non-cacheable region 4, start addr 15-12, size (low nibble) (see #P0018)
SeeAlso: #P0023,#P0021

(Table P0018)
Values for Cyrix Cx486SLC/DLC non-cacheable region sizes:
 00h	disabled
 01h	4K
 02h	8K
 03h	16K
 04h	32K
 05h	64K
 06h	128K
 07h	256K
 08h	512K
 09h	1M
 0Ah	2M
 0Bh	4M
 0Ch	8M
 0Dh	16M
 0Eh	32M
 0Fh	4G
SeeAlso: #P0017

Bitfields for Cyrix Cx486SLC/DLC Configuration Register 0:
Bit(s)	Description	(Table P0019)
 0	"NC0" first 64K of each 1M noncacheable in real/V86
 1	"NC1" 640K-1M noncacheable
 2	"A20M" enables A20M# input pin
 3	"KEN"  enables KEN# input pin
 4	"FLUSH" enables FLUSH input pin
 5	"BARB" enables internal cache flushing on bus holds
 6	"C0" cache direct-mapped instead of 2-way associative
 7	"SUSPEND" enables SUSP# input and SUSPA# output pins
SeeAlso: #P0017,#P0020,#P0032

Bitfields for Cyrix Cx486SLC/DLC Configuration Register 1:
Bit(s)	Description	(Table P0020)
 0	"RPL" enables output pins RPLSET and RPLVAL#
SeeAlso: #P0017,#P0019,#P0024

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P00220023 - PORT 0022-0023 - Cyrix 486S2/D2/DX/DX2/DX4 PROCESSOR - CONFIGURATION REGISTERS

PORT 0022-0023 - Cyrix 486S2/D2/DX/DX2/DX4 PROCESSOR - CONFIGURATION REGISTERS
SeeAlso: PORT 0022h"Cx486SLC",PORT 0022h"5x86",PORT 0022h"6x86"

0022  -W  index for accesses to next port (see #P0021)
0023  RW  cache configuration register array (indexed by PORT 0022h)
	Note:	the index must be written to PORT 0022h before every access
		  to PORT 0023h; out-of-sequence accesses or index values
		  not supported by the processor generate external I/O cycles

(Table P0021)
Values for Cyrix 486S2/D2/DX/DX2/DX4 configuration register number:
 C2h	CR2 (see #P0025)
 C3h	CR3 (see #P0026)
 CDh	SMM region, start address bits 31-24
 CEh	SMM region, start address bits 23-16
 CFh	SMM region, start addr 15-12, size (low nibble) (see #P0018)
 FEh R	Device Identification #0 (see #P0022)
	CPU device ID
 FFh R	Device Identification #1
	bits 3-0: revision
	bits 7-4: stepping
SeeAlso: #P0017,#P0023,#P0031

(Table P0022)
Values for Cyrix device identification:
(#0 /#1)
 00h	Cx486SLC
 01h	Cx486DlC
 02h	Cx486SLC2
 03h	Cx486DLC2
 04h	Cx486SRx
 05h	Cx486DRx
 06h	Cx486SRx2
 07h	Cx486DRx2
 10h	Cx486S (B-step)
 11h	Cx486S2 (B-step)
 12h	Cx486Se (B-step)
 13h	Cx486S2e (B-step)
1Ah/05h	Cx486DX-40
1Bh/08h	Cx486DX2-50
1Bh/0Bh	Cx486DX2-66
1Bh/31h	Cx486DX2-v80
1Fh/36h	Cx486DX4-v100
 28h	5x86 1xs
 29h	5x86 2xs
 2Ah	5x86 1xp
 2Bh	5x86 2xp
 2Ch	5x86 4xs
 2Dh	5x86 3xs
 2Eh	5x86 4xp
 2Fh	5x86 3xp
 30h	6x86 1xs
 31h	6x86 2xs
 32h	6x86 1xp
 33h	6x86 2xp
 34h	6x86 4xs
 35h	6x86 3xs
 36h	6x86 4xp
 37h	6x86 3xp
Note:	#0 is the value in configuration register FEh, while #1 is the value
	  in configuration register FFh
SeeAlso: #P0021

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P00220023 - PORT 0022-0023 - Cyrix 5x86 PROCESSOR - CONFIGURATION CONTROL REGISTERS

PORT 0022-0023 - Cyrix 5x86 PROCESSOR - CONFIGURATION CONTROL REGISTERS
SeeAlso: PORT 0022h"Cx486SLC",PORT 0022h"486S2",PORT 0022h"6x86"

0022  -W  index for accesses to next port (see #P0023)
0023  RW  configuration control register array (indexed by PORT 0022h)
	Note:	the index must be written to PORT 0022h before every access
		  to PORT 0023h; out-of-sequence accesses or index values
		  not supported by the processor generate external I/O cycles

(Table P0023)
Values for Cyrix 5x86 configuration registers:
 20h	Performance Control (see #P0028)
 C1h	Configuration Control #1 (CCR1) (see #P0024)
 C2h	Configuration Control #2 (CCR2) (see #P0025)
 C3h	Configuration Control #3 (CCR3) (see #P0026)
 CDh	System Memory Management address region #0 (smar0) (see #P0029)
 CEh	System Memory Management address region #1 (smar1)
 CFh	System Memory Management address region #2 (smar2)
 E8h	Configuration Control Register 4
 F0h	Power Management (see #P0030)
 FEh R	Device Identification #0 (see #P0022)
	CPU device ID
 FFh R	Device Identification #1
	bits 3-0: revision
	bits 7-4: stepping
SeeAlso: #P0017,#P0021,#P0031

Bitfields for Cyrix 5x86,6x86 Configuration Control Register 1 (CCR1):
Bit(s)	Description	(Table P0024)
 0	reserved
 1	enable SMM pins
 2	system management memory access
 3	main memory access
 4	(6x86) no LOCK during bus cycles
 6-5	reserved
 7	(6x86) use address region 3 as SMM space
Note:	bits 1,2,7 may only be written when CCR3 bit 0 is enabled
SeeAlso: #P0020,#P0025,#P0026,#P0027

Bitfields for Cyrix 5x86,6x86 Configuration Control Register 2 (CCR2):
Bit(s)	Description	(Table P0025)
 0	reserved
 1	enable write-back cache interface pins
 2	lock NW bit
 3	suspend on HLT instruction
 4	write-through region 1
 5	reserved
 6	enable burst write cycles
 7	enable suspend pins
SeeAlso: #P0024,#P0026,#P0027

Bitfields for Cyrix 5x86,6x86 Configuration Control Register 3 (CCR3):
Bit(s)	Description	(Table P0026)
 0	SMM register lock (can only be cleared in SMM mode or by CPU reset)
 1	NMI enable
 2	linear address burst cycles (5x86,6x86 only)
	=0 Pentium-compatible
	=1 linear sequencing
 3	SMM mode (5x86 only)
	=0 486SL
	=1 Cyrix
 7-4	map enable (5x86,6x86 only)
	0000 only allow access to configuration registers C0h-CFh,FEh,FFh
	0001 enable access to all configuration registers
SeeAlso: #P0024,#P0025,#P0027,#P0028,#P0030

Bitfields for Cyrix 5x86,6x86 Configuration Control Register 4 (CCR4):
Bit(s)	Description	(Table P0027)
 2-0	I/O recovery time (000 = none, else 2^N clocks)
 3	enable memory-read bypassing (5x86 only)
 4	enable directory table entry cache
 6-5	reserved
 7	enable CPUID instruction (stepping 1+ and Cx6x86)
Note:	this register is only accessible when bits 7-4 of CCR3 are 0001
SeeAlso: #P0024,#P0025,#P0026

Bitfields for Cyrix 5x86 Performance Control register:
Bit(s)	Description	(Table P0028)
 0	return stack enabled (speculatively execute code after current CALL)
 1	branch-target buffer enabled
 2	loop enable
 6-3	reserved (0)
 7	load-store serialization enabled
	(memory reads and writes may be reorganized into optimum order)
Note:	this register is only accessible when bits 7-4 of CCR3 are 0001
SeeAlso: #P0030,#P0024

Bitfields for Cyrix 5x86 SMM Address Region register:
Bit(s)	Description	(Table P0029)
 3-0	block size
 23-4	starting address

Bitfields for Cyrix 5x86 Power Management register:
Bit(s)	Description	(Table P0030)
 1-0	core clock to bus clock ratio
	00 1:1
	01 2:1
	10 reserved
	11 3:1
 2	CPU running at half bus speed, ignore bits 1-0
Note:	this register is only accessible when bits 7-4 of CCR3 are 0001

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P00220023 - PORT 0022-0023 - Cyrix 6x86 PROCESSOR - CONFIGURATION CONTROL REGISTERS

PORT 0022-0023 - Cyrix 6x86 PROCESSOR - CONFIGURATION CONTROL REGISTERS
SeeAlso: PORT 0022h"Cx486",PORT 0022h"5x86"

0022  -W  index for accesses to next port (see #P0023)
0023  RW  configuration control register array (indexed by PORT 0022h)
	Note:	the index must be written to PORT 0022h before every access
		  to PORT 0023h; out-of-sequence accesses or index values
		  not supported by the processor generate external I/O cycles

(Table P0031)
Values for Cyrix 6x86 configuration registers:
 C0h	Configuration Control Register 0 (CCR0) (see #P0032)
 C1h	Configuration Control #1 (CCR1) (see #P0024)
 C2h	Configuration Control #2 (CCR2) (see #P0025)
 C3h	Configuration Control #3 (CCR3) (see #P0026)
 C4h	Address region 0 (bits 31-24)
 C5h	Address region 0 (bits 23-16)
 C6h	Address region 0 (bits 15-12 and size)
 C7h	Address region 1 (bits 31-24)
 C8h	Address region 1 (bits 23-16)
 C9h	Address region 1 (bits 15-12 and size)
 CAh	Address region 2 (bits 31-24)
 CBh	Address region 2 (bits 23-16)
 CCh	Address region 2 (bits 15-12 and size)
 CDh	Address region 3 (bits 31-24)
 CEh	Address region 3 (bits 23-16)
 CFh	Address region 3 (bits 15-12 and size)
 D0h	Address region 4 (bits 31-24)
 D1h	Address region 4 (bits 23-16)
 D2h	Address region 4 (bits 15-12 and size)
 D3h	Address region 5 (bits 31-24)
 D4h	Address region 5 (bits 23-16)
 D5h	Address region 5 (bits 15-12 and size)
 D6h	Address region 6 (bits 31-24)
 D7h	Address region 6 (bits 23-16)
 D8h	Address region 6 (bits 15-12 and size)
 D9h	Address region 7 (bits 31-24)
 DAh	Address region 7 (bits 23-16)
 DBh	Address region 7 (bits 15-12 and size)
 DCh	Region Control 0
 DDh	Region Control 1
 DEh	Region Control 2
 DFh	Region Control 3
 E0h	Region Control 4
 E1h	Region Control 5
 E2h	Region Control 6
 E3h	Region Control 7
 E8h	Configuration Control Register 4 (see #P0027)
 E9h	Configuration Control Register 5 (see #P0033)
 FEh R	Device Identification #0 (see #P0022)
	CPU device ID
 FFh R	Device Identification #1
	bits 3-0: revision
	bits 7-4: stepping
SeeAlso: #P0017,#P0023

Bitfields for Cyrix 6x86 Configuration Control Register 0:
Bit(s)	Description	(Table P0032)
 7-2	???
 1	address region 640K-1M is noncacheable
 0	???
SeeAlso: #P0019

Bitfields for Cyrix 6x86 Configuration Control Register 5:
Bit(s)	Description	(Table P0033)
 7-6	reserved
 5	enable all address-region registers (control registers C4h-DBh)
 4	assert LBA# pin on all accesses to 640K-1M
 3-1	reserved
 0	allocate new cache lines only on read misses
SeeAlso: #P0032,#P0027,#P0031

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P00220023 - PORT 0022-0023 - GoldStar 286 - CHIP SET CONFIGURATION REGISTERS

PORT 0022-0023 - GoldStar 286 - CHIP SET CONFIGURATION REGISTERS
SeeAlso: PORT 0022h"Cx486SLC",PORT 0022h"486S2",PORT 0022h"6x86"

0022  -W  index for accesses to next port (see #P0034)
0023  RW  configuration control register array (indexed by PORT 0022h)

(Table P0034)
Values for GoldStar 286 chipset configuration register index:
 60h	turbo control
	write 00h to PORT 0023h to turn on turbo, 10h to turn it off

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P00220023 - PORT 0022-0023 - Intel 82358DT 'Mongoose' EISA CHIPSET - 82359 DRAM CONTROLLER

PORT 0022-0023 - Intel 82358DT 'Mongoose' EISA CHIPSET - 82359 DRAM CONTROLLER
Notes:	this chip uses a chip ID of 01
	the LIM register herein use a chip ID of 1A
Index: Intel 82351

0022  -W  index for accesses to data port (see #P0036,#P0037,#P0038)
0023  RW  chip set data

(Table P0035)
Values for Intel 82351/82359 chip ID:
 01h	82359 DRAM controller, general registers
 02h	82351 EISA local I/O support
 A1h	82359 DRAM controller, EMS registers
 FFh	no chip accessible (default)
SeeAlso: #P0036,#P0037,#P0038

(Table P0036)
Values for 82359 DRAM controller general register index:
 00h	DRAM bank 0 type
	bit 7	unknown
	bit 6-4	000 DRAM in bank 0 (standard)
		001 bank 1
		010 bank 2
		011 bank 3
		100 banks 0,1
		101 banks 2,3
		110 banks 0,1,2,3
		111 empty (standard for 1,2,3)
	bit 3-2	unknown
	bit 1-0	00 64K chips used
		01 256K
		10 1M
		11 4M
 01h	DRAM bank 1 type
 02h	DRAM bank 2 type
 03h	DRAM bank 3 type
 04h	DRAM speed detection/selection
 05h	DRAM interleave control
 06h	RAS line mode
 07h	cache-enable selection
 08h	mode register A (DRAM, cache)
 09h	mode register B (cache, burst modes, BIOS size)
 0Ah	mode register C (concurrency control, burst/cycle speed)
 10h	host timing
 11h	host-system delay timing
 12h	system timing
 13h	DRAM row precharge time
 14h	DRAM row timing
 15h	DRAM column timing
 16h	CAS pulse width
 17h	CAS-to-MDS delay
 21h	chip ID register -- selects which chip responds on these ports
	(see #P0035)
 28h-2Ch	parity-error trap address
 30h	page hit cycle length (read)
 31h	page miss cycle length (read)
 32h	row miss cycle length (read)
 33h	page hit cycle length (write)
 34h	page miss cycle length (write)
 35h	row miss cycle length (write)
 40h	memory enable 00000h-7FFFFh
 41h	memory enable 80000h-9FFFFh
 42h	memory enable A0000h-AFFFFh
 43h	memory enable B0000h-BFFFFh
 44h	memory enable C0000h-CFFFFh
 45h	memory enable D0000h-DFFFFh
 46h	memory enable E0000h-EFFFFh
 47h	memory enable F0000h-FFFFFh
 4Eh	remap 80000h-FFFFFh to extended memory
 50h-53h	programmable attribute map 1
 54h-57h	programmable attribute map 2
 58h-5Bh	programmable attribute map 3
 5Ch-5Fh	programmable attribute map 4
 83h-84h	split address register (address bits A31-A20)
 85h	cache control
 8Bh	system throttle
 8Ch	host throttle
 8Dh	host memory throttle watchdog
 8Eh	host system throttle
 8Fh	host system throttle watchdog
 90h	RAM enable
 91h	RAM disable
 92h-93h	elapsed-time registers
 94h-95h	host memory ownership request
 96h-97h	system memory ownership request
 98h-99h	host memory ownership
 9Ah-9Bh	system bus ownership
 9Ch-9Dh	host system bus request
 9Eh-9Fh	memory ownership transfer
SeeAlso: #P0037,#P0038

(Table P0037)
Values for Intel 82359 DRAM controller EMS register index:
 00h	EMS cotnrol
 21h	chip ID register -- selects which chip responds on these ports
	(see #P0035)
 80h-8Fh	EMS page registers, pages 0-7
SeeAlso: #P0036,#P0038

(Table P0038)
Values for Intel 82351 EISA Local I/O register index:
 21h	chip ID register -- selects which chip responds on these ports
	(see #P0035)
 C0h	peripheral enable register A
 C1h	peripheral enable register B
 C2h	parallel configuration register
 C3h	serial configuration register A
 C4h	floppy disk controller configuration register
 C5h	serial configuration register B
 C6h	COM3 port address (low)
 C7h	COM3 port address (high)
 C8h	COM4 port address (low)
 C9h	COM4 port address (high)
 D0h-D3h	general chip select lines 0-3 (mask registers)
 D4h-D7h	general chip select line addresses 0-3 (low bytes)
 D8h-DBh	general chip select line addresses 0-3 (high bytes)
 DCh	extended CMOS RAM page port address (low)
 DDh	extended CMOS RAM page port address (high)
 DFh	extended CMOS RAM access select address (high byte)
 E8h-EBh	EISA ID configuration registers (reflect at PORT 0C80h)
SeeAlso: #P0036,#P0037

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P00220023 - PORT 0022-0023 - Intel 82374EB/SB EISA CHIPSET

PORT 0022-0023 - Intel 82374EB/SB EISA CHIPSET
Index: Intel 82374EB;Intel 82374SB

0022  -W  index for accesses to data port (see #P0039)
0023  RW  chip set data

!!!29047604.pdf pg. 36
(Table P0039)
Values for Intel 82374 register index:
 02h	ESC identification register
	(82374 will only respond to ports 0022h and 0023h after an 0Fh
	 is written to this register)
 08h	revision ID register
 40h	mode select (see #P0040)
 42h	BIOS Chip Select A (see #P0041)
 43h	BIOS Chip Select B (see #P0042)
 4Dh	EISA clock divisor (see #P0043)
 4Eh	peripheral Chip Select A (see #P0044)
 4Fh	peripheral Chip Select B (see #P0045)
 50h-53h EISA ID registers
 57h	scatter/gather relocate base address (see also #01075)
	(specifies bits 15-0 if S/G port addresses [low byte always 10h-3Fh])
 59h	APIC base address relocation
 60h-63h PCI IRQn# route control (see also #01076)
 64h	general-purpose chip select low address 0
 65h	general-purpose chip select high address 0
 66h	general-purpose chip select mask register 0
 68h	general-purpose chip select low address 1
 69h	general-purpose chip select high address 1
 6Ah	general-purpose chip select mask register 1
 6Ch	general-purpose chip select low address 2
 6Dh	general-purpose chip select high address 2
 6Eh	general-purpose chip select mask register 2
 6Fh	general-purpose peripheral X-Bus control
---SB only---
 70h	PCI/APIC control (see #P0046)
 88h	test control
 A0h	SMI control (see #P0047)
 A2h-A3h  SMI enable (see #P0048)
 A4h-A7h  System Event Enable (see #P0049)
 A8h	Fast-Off timer
 AAh-ABh SMI Request (see #P0050)
 ACh	Clock Scale STPCLK# low timer
 AEh	Clock Scale STPCLK# high timer

Bitfields for 82374EB mode select (register 40h):
Bit(s)	Description	(Table P0040)
  7	reserved
  6	enable the selected (MREQ[7:4]#/PIRQ[3:0]# functionality
  5	enable/disable configuration RAM Page Address (CPG[4:0]) generation
	=1 accesses to the configuration RAM space will generate the RAM page
	  address on the LA[31:27]# pins (default)
	=0 the CPG[4:0] signals will not be activated
  4	General Purpose Chip Selects: select GPCS[2:0]#/ECS[2:0] pins' function
	=0 GPCS[2:0]# functionality is selected
	=1 ESC[2:0] functionality is selected
  3	System Error: enable generation of NMI based on SERR# signal pulsing
	=0 NMI is negated and SERR# is disabled from generating an NMI
	=1 NMI signal is asserted when NMIs are enabled via the NMIERTC
	  Register and SERR# is asserted
	Note: other NMI sources are enabled/disabled via the NMISC register
  2-0	PIRQx Mux/Mapping Control: select muxing/mapping of PIRQ[3:0]# with
	  MREQ[7:4] and group of X-Bus signals (DLIGHT#, RTCWR#, RTCRD#).
	Different bit combinations select the number of EISA slots or group of
	  X-Bus signals which can be supported with the certain number of
	  PIRQx# signals by determining the functionality of pins
	  AEN[4:1]/EAEN[4:1], MACK[3:0]#/EMACK[3:0]#, MREQ[7:4]/PIRQ[3:0]#,
	  DLIGHT#/PIRQ0#, FDCCS#/PIRQ1#, RTCWR#/PIRQ2#, and RTCRD#/PIRQ3#.
SeeAlso: #P0039

Bitfields for 82374EB BIOS Chip Select A "BIOSCSA" (register 42h):
Bit(s)	Description	(Table P0041)
  7-6	reserved
  5	Enlarged BIOS: assert LBIOSCS# for memory read cycles to locations
	  FFF80000h-FFFDFFFFh
  4	High BIOS: assert LBIOSCS# for memory read cycles to locations
	  0F0000h-0FFFFFh, FF0000h-FFFFFFh, and FFFF0000h-FFFFFFFFh
  3	Low BIOS 4: assert LBIOSCS# for memory read cycles to locations
	  0EC000h-0EFFFFh, FFEEC000h-FFEEFFFFh, and FFFEC000h-FFFEFFFFh
  2	Low BIOS 3: assert LBIOSCS# for memory read cycles to locations
	  0E8000h-0EBFFFh, FFEE8000h-FFEEBFFFh, and FFFE8000h-FFFEBFFFh
  1	Low BIOS 2: assert LBIOSCS# for memory read cycles to locations
	  0E4000h-0E7FFFh, FFEE4000h-FFEE7FFFh, and FFFE4000h-FFFE7FFFh
  0	Low BIOS 1: assert LBIOSCS# for memory read cycles to locations
	  0E0000h-0E3FFFh, FFEE0000h-FFEE3FFFh, and FFFE0000h-FFFE3FFFh
Note:	if bit 3 of register 43h (BIOSCSB) is set, then LBIOSCS# will be
	  asserted for write cycles as well as read cycles on any enabled range
SeeAlso: #P0039,#P0042

Bitfields for 82374EB BIOS Chip Select B (register 43h):
Bit(s)	Description	(Table P0042)
  7-4	Reserved
  3	BIOS Write Enable: assert LBIOSCS# for both memory read AND write
	  cycles for addresses in the decoded and enabled BIOS range
	  (see #P0041)
  2	16 Meg BIOS: assert LBIOSCS# for memory read cycles to locations
	  FF0000h-FFFFFFh
  1	High VGA BIOS: assert LBIOSCS# for memory read cycles to locations
	  0C4000h-0C7FFFh
  0	Low VGA BIOS: assert LBIOSCS# for memory read cycles to locations
	  0C0000h-0C3FFFh
Note:	if bit 3 of register 43h (BIOSCSB) is set, then LBIOSCS# will be
	  asserted for write cycles as well as read cycles on any enabled range
	  above
SeeAlso: #P0039,#P0041

Bitfields for 82374EB EISA clock divisor (register 4Dh):
Bit(s)	Description	(Table P0043)
  7-6	Reserved
  5	Co-processor Error: specify if the FERR# signal is connected to the
	  ESC internal IRQ13 interrupt signal.
	=0 FERR# signal is ignored by the ESC (i.e. this signal is not
	  connected to any logic in the ESC).
	=1 assert IRQ13 to the interrupt controller if FERR# signal is asserted
  4	82374EB: Reserved
	82374SB: ABFULL (with IRQ12):
	=0 internal IRQ12 is directed to the interrupt controller and 
	  transitions on ABFULL have no effect on this interrupt signal
	=1 the assertion of ABFULL is latched and directed to the internal
	  IRQ12 signal in the following manner:
	    If the interrupt controller is programmed for edge detect mode on
	      IRQ12, a low-to-high transition is generated on the internal
	      IRQ12 signal. Transitions on the IRQ12 input pin are not
	      reflected on the internal IRQ12 signal.
	    If the interrupt controller is programmed for level-sensitive mode,
	      a high-to-low transition is generated on the internal IRQ12
	      signal.  Transitions on the IRQ12 input pin are also reflected
	      on the internal IRQ12 signal.
	The latching of the ABFULL signal is cleared by an I/O read of
	  address 60h (no aliasing) or by a hard reset.
  3	82374EB: Reserved
	82374SB: Keyboard Full (KBFULL): select edge-detect KBFULL function on
	  the IRQ1 input signal
	=0 IRQ1 is directed to the interrupt controller
	=1 (default) IRQ1 is latched and directed to the interrupt controller.
	  The latched IRQ1 is cleared by an I/O read of address 60h (no
	  aliasing) or by a hard reset.
  2-0	Clock Divisor: select the integer used to divide the PCICLK down to
	  generate the BCLK.
	000 4 (33.33 MHz) 8.33 MHz (default after reset)
	001 3 (25 MHz) 8.33 MHz
	01x reserved
	1xx reserved
SeeAlso: #P0039

Bitfields for 82374EB peripheral Chip Select A (register 4Eh):
Bit(s)	Description	(Table P0044)
  7	Reserved
  6	Keyboard Controller Mapping
	=0 the keyboard controller encoded chip select signal and the X-Bus
	  transceiver enable (XBUSOE#) are generated for accesses to address
	  locations 60h (82374EB/SB), 62h (82374EB only), 64h (82374EB/SB) and
	  66h (82374EB only).
	=1 the keyboard controller chip select signals are generated for
	  accesses to the above address locations. However XBUSOE# is disabled.
	Note:	bit 1 must be 1 for either value of this configuration bit to
		  decode an access to locations 60h, 62h, 64h, or 66h.
  5	Floppy Disk/IDE Controller Address range
	=0 primary (1Fxh and 3Fxh)
	=1 secondary (17xh and 37xh)
  4	IDE DECODE: enable or disable IDE locations 1F0h-1F7h (primary) or
	  170h-177h (secondary) and 3F6h,3F7h (primary) or 376h,377h (sec).
	82374EB: When this bit is set to 0, the IDE encoded chip select signals
	  and the X-Bus transceiver signal (XBUSOE#) are not generated for
	  these addresses.
	82374SB: When this bit is set to 0, the IDE encoded chip select signals
	  and the X-Bus transceiver signal (XBUSOE#) are not generated for
	  addresses 1F0h-1F7h (primary) or 170h-177h (secondary) and 3F6h or
	  376h.	 Read/write accesses to addresses 377h and 3F7h are not
	  disabled and still generate XBUSOE#.
  3-2	Floppy Disk and IDE/Floppy Disk Decodes: Bits 2 and 3 are used to
	  enable or disable the floppy locations as indicated. Bit 2 defaults
	  to enabled (1) and bit 3 defaults to disabled (0) when a reset occurs
  1	Keyboard Controller Decode: enable the keyboard controller address
	  locations 60h (82374EB/SB), 62h (82374EB only), 64h (82374EB/SB), and
	  66h (82374EB only).
	=0 the keyboard controller encoded chip select signals and the X-Bus
	  transceiver signal (XBUSOE#) are not generated for these locations
	Note:	the value of this bit affects control function (keyboard
		  controlling mapping) provided by bit 6 of this register.
  0	Real Time Clock Decode: enable the RTC address locations 70h-77h.
	=0 the RTC encoded chip	select signals RTCALE, RTCRD, RTCWR#, and
	  XBUSOE# signals are not generated for these addresses.
SeeAlso: #P0039,#P0045

Bitfields for 82374EB peripheral Chip Select B (register 4Fh):
Bit(s)	Description	(Table P0045)
  7	CRAM Decode: enable I/O write accesses to location 0C00h and I/O
	  read/write accesses to locations 0800h-08FFh. The configuration RAM
	  read and write (CRAMRD#, CRAMWR#) strobes are valid for accesses to
	  0800h-08FFh.
  6	Port 92 Decode: enable access to Port 92 (default at PCIRST is enabled)
  5-4	select which Parallel Port address range (LPT1, 2, or 3) is decoded.
	00 LPT1 (3BCh-3BFh)
	01 LPT2 (378h-37Fh)
	10 LPT3 (278h-27Fh)
	11 disabled
  3-2	Serial Port B Address Decode: If either COM1 or COM2 address ranges
	  are selected, these bits default to disabled upon PCIRST.
	00 3F8h-3FFh (COM1)
	01 2F8h-2FFh (COM2)
	10 Reserved
	11 Port B disabled
  1-0	Serial Port A Address Decode: If either COM1 or COM2 address ranges are
	  selected, these bits default to disabled upon PCIRST.
	00 3F8h-3FFh (COM1)
	01 2F8h-2FFh (COM2)
	10 Reserved
	11 Port A disabled
SeeAlso: #P0039,#P0044

Bitfields for 82374SB PCI/APIC control (register 70h):
Bit(s)	Description	(Table P0046)
  7-2	Reserved
  1	SMI Routing Control (SMIRC)
	=1 SMI is routed via the APIC
	=0 SMI is routed via the SMI# signal
	Note:	when SMRCe1, INTR can not be routed through the APIC, since it
		  is sharing the APIC interrupt input with SMI#.
  0	INTR Routing Control (INTRC): When APIC is enabled (in mixed or pure
	  APIC mode), this bit allows the ESC's external INTR signal to be
	  masked (forces INTR to the inactive state but does not tri-states
	  the signal). Thus, the CPU's INTR pin can be used (by providing a
	  simple -gate) for the APIC Local Interrupt (LINTRx). However, INTR
	  must not be masked via this bit when APIC is disabled and INTR is
	  the only mechanism to signal the 8259 recognized interrupts to the
	  CPU.
	=1 INTR is disabled (APIC must be enabled)
	=0 INTR is enabled
SeeAlso: #P0039

Bitfields for 82374SB SMI control (register A0h):
Bit(s)	Description	(Table P0047)
  7	reserved (0)
  6-4	reserved
  3	Fast Off Timer Freeze (CTMRFRZ): disable the Fast Off Timer
	Disabling the timer prevents time-outs from occurring while executing
	  SMM code.
  2	STPCLK# Scaling Enable (CSTPCLKSC)
	=0 (default) scaling control of the STPCLK# signal is disabled.
	=1, the STPCLK# signal scaling control is enabled. When enabled (and
	  bit 1=1, enabling the STPCLK# signal), the high and low times for the
	  STPCLK# signal are controlled by the Clock Scaling STPCLK# High Timer
	  and Clock Scaling STPCLK# Low Timer Registers, respectively.
  1	STPCLK# Signal Enable (CSTPCLKE): permits software to place the CPU
	  into a low power state.
	=0 (default) STPCLK# signal is disabled and is negated (high)
	=1 the STPCLK# signal is enabled and a read from the APMC Register
	  causes STPCLK# to be asserted
	Software can set this bit to 0 by writing a 0 to it or by any write to
	  the APMC Register.
  0	SMI# Gate (CSMIGATE)
	=0 (default) the SMI# signal is masked and negated
	=1 SMI# signal is enabled and a system management interrupt condition
	  causes the SMI# signal to be asserted
Note:	bit 0 only affects the SMI# signal and does not affect the
	  detection/recording of SMI events (i.e., it does not affect the SMI
	  status bits in the SMIREQ Register). Thus, SMI conditions can be
	  pending when bit 0 is set to 1; if an SMI is already pending, the
	  SMI# signal is asserted.
SeeAlso: #P0039

Bitfields for 82374SB SMI enable (register A2h-A3h):
Bit(s)	Description	(Table P0048)
  15-8	Reserved
  7	APMC Write SMI Enable
	=0 writes to the APMC Register do not generate an SMI
	=1 writes to the APMC Register generate an SMI
  6	EXTSMI# SMI Enable
	=1 asserting the EXTSMI# input signal generates an SMI
  5	Fast Off Timer SMI Enable
	=1 Fast-Off timer generates an SMI when it decrements to zero
  4	IRQ12 SMI Enable (PS/2 Mouse Interrupt)
	=1 asserting the IRQ12 input signal generates an SMI
  3	IRQ8 SMI Enable (RTC Alarm Interrupt)
	=1 asserting the IRQ8 input signal generates an SMI
  2	IRQ4 SMI Enable (COM2/COM4 Interrupt or Mouse)
	=1 asserting the IRQ3 input signal generates an SMI
  1	IRQ3 SMI Enable (COM1/COM3 Interrupt or Mouse)
	=1 asserting the IRQ3 input signal generates an SMI
  0	IRQ1 SMI Enable (Keyboard Interrupt)
	=1 asserting the IRQ1 input signal generates an SMI
SeeAlso: #P0039

Bitfields for 82374SB System Event Enable (register A4h-A7h):
Bit(s)	Description	(Table P0049)
  31	Fast Off SMI Enable (FSMIEN)
	=1 an SMI causes a system event that re-loads the Fast Off Timer and a
	  break event that negates the STPCLK# signal
	=0 an SMI does not re-load the Fast Off Timer or negate the STPCLK#
	  signal
  30	reserved
  29	Fast Off NMI Enable (FNMIEN)
	=1 an NMI (e.g., parity error) causes a system event that re-loads the
	  Fast Off Timer and a break event that negates the STPCLK# signal
	=0 an SMI does not re-load the Fast Off Timer or negate	the STPCLK#
	  signal.
  28-16 reserved
  15-3	These bits are used to prevent the system from entering Fast Off and
	  break any current powerdown state when the selected hardware
	  interrupt (IRQ15-IRQ3) occurs
	=1 the corresponding interrupt causes a	system event that re-loads the
	  Fast Off Timer and a break event that	negates the STPCLK# signal
	=0 the corresponding interrupt does not re-load the Fast Off Timer or
	  negate the STPCLK# signal
  2	reserved
  1-0	These bits are used to prevent the system from entering Fast Off and
	  break any current powerdown state when the selected hardware
	  interrupt (IRQ1-IRQ0) occurs
	=1 the corresponding interrupt causes a	system event that re-loads the
	  Fast Off Timer and a break event that	negates the STPCLK# signal
	=0 the corresponding interrupt does not re-load the Fast Off Timer or
	  negate the STPCLK# signal
SeeAlso: #P0039

Bitfields for 82374SB SMI Request (register AAh-ABh):
Bit(s)	Description	(Table P0050)
  15-8	Reserved
  7	APM SMI Status (RAPMC): set to 1 to indicate that a write to the APM
	  Control Register caused an SMI
  6	EXTSMI# SMI Status (REXT): set to 1 when EXTSMI# caused an SMI
  5	Fast Off Timer Expired Status (RFOT): set to 1 to indicate that the
	  Fast Off Timer expired and caused an SMI.  The Fast Off  timer
	  re-starts counting on the next clock after it expires.
  4	SMI caused by IRQ12
  3	SMI caused by IRQ8
  2	SMI caused by IRQ4
  1	SMI caused by IRQ3
  0	SMI caused by IRQ1
SeeAlso: #P0039

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P00220023 - PORT 0022-0023 - CHIPSET FROM ETEC CHEETAH ET6000 (SINGLE CHIP)

PORT 0022-0023 - CHIPSET FROM ETEC CHEETAH ET6000 (SINGLE CHIP)

0022  RW  chip set data
0023  ?W  index for accesses to data port (see #P0051)

(Table P0051)
Values for Etec Cheetah ET6000 chip set register index:
 10h	system configuration register (see #P0052)
 11h	cache configuration & non-cacheable block size register (see #P0053)
 12h	non-cacheable block address register
	bit 7-1	non-cacheable address, A25-A19
	bit 0	reserved
 13h	DRAM bank & type configuration register (see #P0054)
 14h	DRAM configuration register (see #P0055)
 15h	shadow RAM configuration register (see #P0056)

Bitfields for Etec Cheetah ET6000 system configuration register:
Bit(s)	Description	(Table P0052)
 7-6	00 turbo/non-turbo
	01 local device supported
	10 suspend mode
	11 illegal
 5	reserved
 4	refresh selection
	0 = AT type refresh
	1 = concurrent refresh
 3	slow refresh  95mSec enabled
 2	fast reset delay
	0 = do not use delay
	1 = wait for 2mSec delay
 1	wait for HALT after KBDRST
 0	RAM at A0000-BFFFF
	0 = AT bus cycle
	1 = local bus cycle
SeeAlso: #P0051

Bitfields for Etec Cheetah ET6000 cache configuration register:
Bit(s)	Description	(Table P0053)
 7-5	000 disabled
	001 512K
	010 1M
	011 2M
	100 4M
	101 8M
	110 16M
	111 32M
 4	DRAM banks
	0 = 2-bank DRAM
	1 = 4-bank DRAM
 3-0	reserved
SeeAlso: #P0051

Bitfields for Etec Cheetah ET6000 DRAM bank & type configuration register:
Bit(s)	Description	(Table P0054)
 7-6	bank 3 DRAM type
	00 none
	01 256K
	10 1M
	11 4M
 5-4	bank 2 DRAM type
 3-2	bank 1 DRAM type
 1-0	bank 0 DRAM type
SeeAlso: #P0051

Bitfields for Etec Cheetah ET6000 DRAM configuration register:
Bit(s)	Description	(Table P0055)
 7	on-board memory range 15M to 16M disabled
 6	on-board memory range 512K-640K disabled
 5	ROM chip select at C0000-DFFFF enabled
 4	RAS to CAS time
	0 = 1 SYSCLCK,	not for R0WS
	1 = 2 SYSCLCK
 3	RAS precharge time
	0 = 1.5 SYSCLCK
	1 = 2.5 SYSCLCK
 2-1	read cycle wait state
	00 = 0 wait state
	01 = 1 ws
	10 = 2 ws
	11 = 3 ws
 0	write cycle wait state
	0 = 0 ws
	1 = 1 ws
SeeAlso: #P0051

Bitfields for Etec Cheetah ET6000 shadow RAM configuration register:
Bit(s)	Description	(Table P0056)
 7	shadow at C0000-FFFFF
	0 = non-cacheable
	1 = cacheable and cache-write-proteced
 6	access ROM/RAM at F0000-FFFFF
	0 = read from ROM, write to RAM
	1 = read from shadow, write is protected
 5	access ROM/RAM at E0000-EFFFF
	0 = access on-board ROM, AT bus cycle
	1 = access shadow E0000-EFFFF enabled
 4	RAM at E0000-EFFFF is read-only
 3	access ROM/RAM at D0000-DFFFF
	0 = access on-board ROM, AT bus cycle
	1 = access shadow D0000-DFFFF enabled
 2	RAM at D0000-DFFFF is read-only
 1	access ROM/RAM at C0000-CFFFF
	0 = access on-board ROM, AT bus cycle
	1 = access shadow C0000-CFFFF enabled
 0	RAM at C0000-CFFFF is read-only
SeeAlso: #P0051

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P00220023 - PORT 0022-0023 - Hewlett-Packard Hornet chipset (HP 100LX/200LX)

PORT 0022-0023 - Hewlett-Packard Hornet chipset (HP 100LX/200LX)

0022  RW  index for accesses to data port (see Table P189)
0023  RW  chip set data

(Table P0057)
Values for HP Hornet chipset register index:
 1Eh	buzzer volume/clock oscillator speed
	bit 7-6: buzzer volume
	bit 5-4: system oscillator speed
		00: 10.738636MHz
		01: 15.836773MHz(HP 100/200LX has oscillator with this speed)
		10: 21.477272MHz
		11: 31.673550MHz
 21h	display timing???
 23h	LCD contrast (see INT15h AH=62h)
	valid values: 00h-1fh (1fh is the darkest)
 51h	power adapter status
	bit 7-1: ???
	bit 0: power adapter status(0=inactive/1=active)
 52h	nicad charge status
	bit 7-3: ???
	bit 2: battery charging status(0=???/1=slow charge)
	bit 1-0: ???
 53h	nicad charge status
	bit 7-1: ???
	bit 0: battery charging status(0=???/1=fast charge)
 80h	memory wait for internal ROM
	valid values: 00h-07h
 81h	memory wait for internal RAM
	valid values: 00h-03h
 82h	memory wait for external RAM
	valid values: 00h-0fh
 87h	battery status???

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P00220023 - PORT 0022-0023 - Chips&Technologies 82C100/110 - CONFIGURATION REGISTERS

PORT 0022-0023 - Chips&Technologies 82C100/110 - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)

0022  -W  configuration register index (see #P0058)
0023  RW  configuration register data

(Table P0058)
Values for Chips&Technologies 82C100/110 configuration register index:
 40h	clock mode/size (see #P0059)
 41h	system configuration (see #P0060)
 42h	configuration valid (see #P0061)
 43h	DIP switch emulation (see #P0062)
 44h-47h substitute NMI vector, bytes 0-3
	(these specify the vector to be substituted at the INT 02 vector's
	  memory address whenever an NMI occurs, preventing application
	  software from modifying the NMI handler)
 48h	refresh timer counter (see #P0063)
 49h	wait state select, refresh enable, keyboard type (see #P0064)
 4Ah	reserved
 4Bh	sleep/memory configuration (see #P0065)
 4Ch	EMS configuration (see #P0066)
 4Dh-4Fh reserved

Bitfields for Chips&Technologies 82C100 clock mode/size register:
Bit(s)	Description	(Table P0059)
 !!!
!!!chips\82c110.pdf p.35
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C100 system configuration register:
Bit(s)	Description	(Table P0060)
 !!!
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C100 configuration valid register:
Bit(s)	Description	(Table P0061)
 !!!
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C110 DIP Switch Emulation register:
Bit(s)	Description	(Table P0062)
 !!!chips\82c110.pdf p.36
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C100 refresh timer count register:
Bit(s)	Description	(Table P0063)
 !!!
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C100 wait state select register:
Bit(s)	Description	(Table P0064)
 !!!
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C100 sleep/memory configuration:
Bit(s)	Description	(Table P0065)
 !!!
SeeAlso: #P0058

Bitfields for Chips&Technologies 82C100 EMS configuration register:
Bit(s)	Description	(Table P0066)
 !!!
SeeAlso: #P0058

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P00220023 - PORT 0022-0023 - Chips&Technologies 82C235 "SCAT" - CONFIGURATION REGISTERS

PORT 0022-0023 - Chips&Technologies 82C235 "SCAT" - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)

0022  -W  configuration register index (see #P0067)
0023  RW  configuration register data

(Table P0067)
Values for Chips&Technologies 82C235 configuration register index:
 01h	DMA wait-state control
 40h	version (read-only)
 41h	clock control
 42h-43h reserved (but listed as read-write in docs)
 44h	peripheral control
 45h	miscellaneous status
 46h	power management
 47h	reserved
 48h	ROM enable
 49h	RAM write-protect control
 4Ah	shadow RAM enable 1
 4Bh	shadow RAM enable 2
 4Ch	shadow RAM enable 3
 4Dh	DRAM configuration
 4Eh	extended boundary
 4Fh	EMS control
 !!!chips\82c235.pdf p.87, p.140

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P00220023 - PORT 0022-0023 - Chips&Technologies 82C311 - CONFIGURATION REGISTERS

PORT 0022-0023 - Chips&Technologies 82C311 - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)

0022  -W  configuration register index (see #P0068)
0023  RW  configuration register data

(Table P0068)
Values for Chips&Technologies 82C311 configuration register index:
 04h	version (read-only)   !!!chips\82c311.pdf p.65
 05h	AT-bus command delay
 06h	AT-bus wait-state control
 08h	identification
 09h	low RAM/ROM configuration
 0Ch	memory enable map (80000h-9FFFFh)
 0Dh	memory enable map (A0000h-BFFFFh)
 0Eh	memory enable map (C0000h-DFFFFh)
 0Fh	memory enable map (E0000h-FFFFFh)
 10h	block 0 type and start address
 11h	block 0 DRAM timing
 12h	block 1 type and start address
 13h	block 1 DRAM timing
 14h	block 2 type and start address
 15h	block 2 DRAM timing
 16h	block 3 type and start address
 17h	block 3 DRAM timing
 18h	memory block types
 20h	cache control
 21h	directory RAM control 1
 22h	tag RAM directory address (low)
 23h	reference location
 24h	SRAM configuration/direct access address
 25h	directory RAM control 2
 26h	READY timeout
 28h	error source/address
 29h	error address (bits 23-16)
 2Ah	memory enable map (00000h-7FFFFh)
 2Bh	miscellaneous control
 2Ch	middle RAM/ROM configuration
 2Fh	page mode posted-write control (82C311 rev. C only)
 30h	block 0 non-cacheable address (bits 23-16)
 31h	block 0 non-cacheable address (bits 15-12) and size
 32h	block 1 non-cacheable address (bits 23-16)
 33h	block 1 non-cacheable address (bits 15-12) and size
 34h	block 2 non-cacheable address (bits 23-16)
 35h	block 2 non-cacheable address (bits 15-12) and size
 36h	block 3 non-cacheable address (bits 23-16)
 37h	block 3 non-cacheable address (bits 15-12) and size
 38h	block 0/1 non-cacheable addresses (bits 26-24)
 39h	block 2/3 non-cacheable addresses (bits 26-24)
 60h	fast reset control
!!!chips\82c311.pdf p.76, p.115

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P00220023 - PORT 0022-0023 - Chips&Technologies 82C315 - CONFIGURATION REGISTERS

PORT 0022-0023 - Chips&Technologies 82C315 - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)
SeeAlso: PORT 0022h"82C311",PORT 0022h"82C316"

0022  -W  configuration register index (see #P0069)
0023  RW  configuration register data

(Table P0069)
Values for Chips&Technologies 82C315 configuration register index:
 07h	processor and bus clock source selection (see #P0070)

Bitfields for C&T 82C315 clock source selection register:
Bit(s)	Description	(Table P0070)
 7-5	reserved (0)
 4	80387 is present
 3	processor clock select
	=0 CLK2IN
	=1 AT bus state machine clock
 2-0	bus clock source select
	000 CLK2IN/5
	001 CLK2IN/4
	010 CLK2IN/3
	011 CLK2IN/2
	100 ATCLK
SeeAlso: #P0069

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P00220023 - PORT 0022-0023 - Chips&Technologies 82C316 - CONFIGURATION REGISTERS

PORT 0022-0023 - Chips&Technologies 82C316 - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)
SeeAlso: PORT 0022h"82C311",PORT 0022h"82C315",PORT 0022h"82C811"

0022  -W  configuration register index (see #P0071)
0023  RW  configuration register data

(Table P0071)
Values for Chips&Technologies 82C316 configuration register index:
 01h	clock/wait-state control	!!!chips\cs8233.pdf p.178
 26h	RTC/NMI/Coprocessor reset	!!!chips\cs8233.pdf p.231
 71h	programmable I/O port 1 address, bits 15-8
 72h	programmable I/O port 1 address, bits 7-0
 73h	programmable I/O port 1 enable
 74h	programmable I/O port 2 address, bits 15-8
 75h	programmable I/O port 2 address, bits 7-0
 76h	programmable I/O port 2 enable
 77h	programmable I/O port 3 address, bits 15-8
 78h	programmable I/O port 3 address, bits 7-0
 79h	programmable I/O port 3 enable
SeeAlso: #P0069

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P00220023 - PORT 0022-0023 - Chips&Technologies 82C811/82C812 - CONFIGURATION REGISTERS

PORT 0022-0023 - Chips&Technologies 82C811/82C812 - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)
SeeAlso: PORT 0022h"82C311",PORT 0022h"82C315"

0022  -W  configuration register index (see #P0072)
0023  RW  configuration register data

(Table P0072)
Values for Chips&Technologies 82C811/812 configuration register index:
 60h	(82C811) processor clock select (see #P0073)
 61h	(82C811) command delay (see #P0074)
 62h	(82C811) wait states (see #P0075)
---82C812---
 64h	version (see #P0076)
 65h	ROM configuration
 66h	memory enable 1
 67h	memory enable 2
 68h	memory enable 3
 69h	memory enable 4
 6Ah	bank 0/1 enable
 6Bh	memory configuration
 6Ch	bank 2/3 enable
 6Dh	EMS base address
 6Eh	EMS address extension
 6Fh	miscellaneous
!!!chips\cs8281.pdf p.48

Bitfields for C&T 82C811 processor clock select:
Bit(s)	Description	(Table P0073)
 7-6	82C811 release number (00 = initial release)
 5	fast CPU reset initiated by changing this bit from 0 to 1
 4	processor clock
	0 CLK2IN (default)
	1 BCLK
 3	reserved
 2	enable NMI generate on timeout of local-bus READY# signal
 1	reserved
 0	local-bus READY# signal timed out (128 clock cycles0
SeeAlso: #P0072,#P0074,#P0075

Bitfields for C&T 82C811 command delay register:
Bit(s)	Description	(Table P0074)
 7	enable additional address bus hold time
 6	reserved (1)
 5-4	AT-bus 16-bit memory access delay, in BCLK cycles (default = 0)
 3-2	AT-bus 8-bit memory access delay, in BCLK cycles (default = 1)
 1-0	I/O command delay, in BCLK cycles (default = 1)
SeeAlso: #P0072,#P0073,#P0075

Bitfields for C&T 82C811 wait states register:
Bit(s)	Description	(Table P0075)
 7	80387sx is present
 6	coprocessor is ready
 5-4	AT-bus 16-bit cycle wait states (default = 3)
 3-2	AT-bus 8-bit cycle wait states (00=two ... 11=five [default])
 1-0	bus clock (BCLK)
	00 CLK2IN/2 (default)
	01 CLK2IN/3
	10 ATCLK
	11 reserved
SeeAlso: #P0072,#P0073,#P0074

Bitfields for C&T 82C812 version register:
Bit(s)	Description	(Table P0076)
 7	NEATsx memory controller (0 = 82C812)
 6-5	82C812 revision (00 = initial release)
 4-0	reserved
SeeAlso: #P0072

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P00220023 - PORT 0022-0023 - Chips&Technologies 84031/84035 - CONFIGURATION REGISTERS

PORT 0022-0023 - Chips&Technologies 84031/84035 - CONFIGURATION REGISTERS
Note:	each access to PORT 0023h must immediately follow a write to
	  PORT 0022h (this is to avoid accidental accesses)
SeeAlso: PORT 0022h"82C311",PORT 0022h"82C315"

0022  -W  configuration register index (see #P0077)
0023  RW  configuration register data

(Table P0077)
Values for Chips&Technologies 84031/84035 configuration register index:
 01h	(84035) IPC DMA controller wait states and clock (see #P0078)
!!!chips\82310.pdf p.71
!!!chips\api22.pdf p.33
 05h	(84031) ISA-bus command delays (see #P0079)
 06h	(84031) ISA-bus wait states (see #P0080)
 07h	(84031) ISA-bus clock select (see #P0081)
 08h	(84035) performance control (see #P0082)
 09h	(84035) miscellaneous control (see #P0083)
 0Ah	(84035) DMA clock select (see #P0084)
 10h	(84031) DRAM timing (see #P0085)
!!!chips\api22.pdf p.49
 11h	(84031) DRAM setup
 12h	(84031) block 0/1 DRAM configuration
 13h	(84031) block 2/3 DRAM configuration
 14h	(84031) DRAM block 0 start address
 15h	(84031) DRAM block 1 start address
 16h	(84031) DRAM block 2 start address
 17h	(84031) DRAM block 3 start address
 18h	(84031) video shadow / local bus control
 19h	(84031) shadow RAM read enable
 1Ah	(84031) shadow RAM write enable
 1Bh	(84031) ROMCS enable
 1Ch	(84031) soft reset / GATEA20

Bitfields for C&T 84035 IPC DMA controller configuration:
Bit(s)	Description	(Table P0078)
 7-6	reserved
 5-4	wait states for 16-bit DMA
	00 one (default)
	01 two
	10 three
	11 four
 3-2	wait states for 8-bit DMA (settings same as bits 5-4)
 1	disable one-cycle delay of MEMR# signal	after IOR#
 0	DMA clock (0 = BUSCLK/2 [default], 1 = BUSCLK)
SeeAlso: #P0077,#P0082

Bitfields for C&T 84031 ISA-bus command delays:
Bit(s)	Description	(Table P0079)
 !!!
SeeAlso: #P0077,#P0080,#P0081

Bitfields for C&T 84031 ISA-bus wait states:
Bit(s)	Description	(Table P0080)
 !!!
SeeAlso: #P0077,#P0079,#P0081

Bitfields for C&T 84031 ISA-bus clock select:
Bit(s)	Description	(Table P0081)
 !!!
SeeAlso: #P0077,#P0079,#P0080

Bitfields for C&T 84035 performance control:
Bit(s)	Description	(Table P0082)
 7	flush 486 cache during every slow-mode hold (keeps CPU from running out
	  of L1 cache during holds)
 6-0	width of CPU hold pulse in BUSCLKs (0-127)
SeeAlso: #P0077,#P0078,#P0083

Bitfields for C&T 84035 miscellaneous control:
Bit(s)	Description	(Table P0083)
 7	floating-point error mode
	=0 generate IRQ13 internally on FERR#
	=1 use external logic to generate IRQ13
 6	keyboard interrupt mode
	=0 receive IRQ1 directly on IRQ1 pin
	=1 receive IRQ1 over control link
 5	disable GATEA20 emulation
	=0 A20 controlled solely by PORT 0092h
	=1 A20 is OR of PORT 0092h and emulated 8042 A20 control
 4	A20M#/TEST# function
	=0 pin is TEST# input
	=1 pin is A29M# output
 3	reserved
 2	enable 8254 Timer 1 refresh requests
	clearing this bit prevents problems that may be caused by a refresh
	  request which occurs during a reset sequence
 1	use VL-bus-compatible preemptive arbitration for LGNT#
 0	deturbo mode (enable CPU holds as specified by performance-control
	  register) (see #P0082)
Note:	the documentation says that bit 6 should remain clear
SeeAlso: #P0077,#P0082

Bitfields for C&T 84035 DMA clock select:
Bit(s)	Description	(Table P0084)
 7	disable internal real-time clock
 6-4	reserved (0)
 3-0	DMA clock
	0000 SCLK/10
	0001 SCLK/8
	0010 SCLK/6
	1000 SCLK/5 (use with 40 MHz SCLK)
	1001 SCLK/4 (use with 33 MHz SCLK)
	1010 SCLK/3 (use with 25 MHz SCLK)
	1011 SCLK/2.5 (for 20 MHz SCLK)
	1100 SCLK/2 (for 16 MHz SCLK)
	1101 SCLK/1.5
	else reserved
Note:	bits 3-0 should normally be set the same as register 07h bits 3-0
SeeAlso: #P0077

Bitfields for C&T 84031 DRAM timing:
Bit(s)	Description	(Table P0085)
 7-6	reserved (0)
 5
 4
 3
 2	!!!
 1	reserved (0)
 0	read timing
	0 = 3-2-2-2
	1 = 4-3-3-3
SeeAlso: #P0077,#P0086

Bitfields for C&T 84031 DRAM setup:
Bit(s)	Description	(Table P0086)
 7	enable DRAM parity
	(PORT 0061h bits 7 and 2 must also both be clear to enable parity)
 6-4	reserved (0)
 3-0	enable interleave for banks 3-0
	(enabling interleave doubles address range for bank; banks 0/2 and 1/3
	  may be interleaved with each other)
SeeAlso: #P0077,#P0085

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P00220023 - PORT 0022-0023 - OPTi 82C206 chipset - CONFIGURATION REGISTERS

PORT 0022-0023 - OPTi 82C206 chipset - CONFIGURATION REGISTERS
Note:	many other OPTi chipsets integrate the functionality of the 82C206, and
	  thus support the 82C206's configuration register (e.g. the
	  82C558 from the Viper chipset)

0022  ?W  index for accesses to data port (set to 01h)
0023  RW  chip set data

Bitfields for OPTi 82C206 configuration register 01h:
Bit(s)	Description	(Table P0087)
 7-6	82C206 wait states
	00 1 SYSCLK
	01 2 SYSCLKs
	10 3 SYSCLKs
	11 4 SYSCLKs (default)
 5-4	number of wait states for 16-bit DMA cycles
	00 1 wait state (default)
	01 2 wait states
	10 3 wait states
	11 4 wait states
 3-2	number of wait states for 8-bit DMA cycles
	00 1 wait state (default)
	01 2 wait states
	10 3 wait states
	11 4 wait states
 1	enable early DMAMEMR#
 0	DMA speed
	0 SYSCLK/2
	1 SYSCLK

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P00220023 - PORT 0022-0023 - Intel 82091AA Advanced Integrated Peripheral

PORT 0022-0023 - Intel 82091AA Advanced Integrated Peripheral
Range:	PORT 0022h (X-Bus), PORT 0024h (X-Bus), PORT 026Eh (ISA), or
	  PORT 0398h (ISA)
SeeAlso: PORT 0024h"82091AA",PORT 026Eh"82091AA",PORT 0398h"82091AA"

0022  ?W  configuration register index (see #P0088)
0023  RW  configuration register data

(Table P0088)
Values for Intel 82091AA configuration register index:
 00h	product ID (read-only)
	A0h Intel 82091AA
 01h	product revision (read-only) (see #P0089)
 02h	configuration 1 (see #P0090)
 03h	configuration 2 (see #P0091)
 04h-0Fh reserved
 10h	floppy-disk controller configuration (see #P0092)
 11h	floppy-disk controller power management/status (see #P0093)
 12h-1Fh reserved
 20h	parallel port configuration (see #P0094)
 21h	parallel port power management/status (see #P0095)
 22h-2Fh reserved
 30h	serial port A configuration (see #P0096)
 31h	serial port A power management/status (see #P0097)
 32h-3Fh reserved
 40h	serial port B configuration (see #P0096)
 41h	serial port B power management/status (see #P0097)
 42h-4Fh reserved
 50h	IDE configuration (see #P0098)
 51h-FFh reserved

Bitfields for Intel 82091AA product revision register:
Bit(s)	Description	(Table P0089)
 7-4	stepping number 
 3-0	"dash"-number
SeeAlso: #P0088

Bitfields for Intel 82091AA configuration register 1:
Bit(s)	Description	(Table P0090)
 7	unused (0)
 6	supply voltage (read-only) (1 = 3.3V, 0 = 5.0V)
 5-4	configuration mode
	00 software motherboard
	01 software add-in
	10 extended hardware
	11 basic hardware
 3	configuration address (read-only)
	0 primary address (PORT 0022h for X-Bus, PORT 026Eh for ISA)
	1 secondary address (PORT 0024h for X-Bus, PORT 0398h for ISA)
 2-1	reserved
 0	power-down AIP's main clock circuitry
SeeAlso: #P0088,#P0091

Bitfields for Intel 82091AA configuration register 2:
Bit(s)	Description	(Table P0091)
 7-3	IRQ7-IRQ3 mode select
	0 = active high (ISA-compatible tri-state drive)
	1 = active low (EISA-compatible open-collector drive)
 2-0	reserved
SeeAlso: #P0088,#P0090

Bitfields for Intel 82091AA floppy-disk controller configuration register:
Bit(s)	Description	(Table P0092)
 7	four floppy drive support enabled (with external decoder)
 6-2	reserved
 1	FDC address
	0 = primary (03F0h)
	1 = secondary (0370h)
 0	enable FDC
SeeAlso: #P0088,#P0093

Bitfields for Intel 82091AA floppy-disk controller power management register:
Bit(s)	Description	(Table P0093)
 7-4	reserved
 3	enable FDC auto-powerdown on idle
 2	reset FDC
	(this bit must be pulsed, remaining high for at least 1.2 us)
 1	(read-only) FDC is idle
 0	power-down FDC
Note:	to restore FDC from explicit powerdown via bit 0, clear bit 0, then
	  reset the FDC using bit 2 (hardware reset) or using a software reset
	  (FDC's DOR bit 2 or DSR bit 7)
SeeAlso: #P0088,#P0092

Bitfields for Intel 82091AA parallel port configuration:
Bit(s)	Description	(Table P0094)
 7	FIFO threshold
	0 = 8 slots in each direction
	1 = one slot forward, 15 reverse
 6-5	parallel-port hardware mode
	00 ISA-compatible
	01 PS/2-compatible
	10 EPP
	11 ECP (read only -- ECP mode must be set via ECP Extended Control Reg)
 4	reserved
 3	IRQ select
	0 = IRQ5
	1 = IRQ7
 2-1	address select
	00 PORT 0378h-037Bh
	01 PORT 0278h-027Bh
	10 PORT 03BCh-03BEh (not for EPP mode)
	11 reserved
 0	enable parallel port
SeeAlso: #P0088,#P0095,#P0920,PORT 0678h"ECP"

Bitfields for Intel 82091AA parallel port power managment register:
Bit(s)	Description	(Table P0095)
 7-6	reserved
 5	FIFO overrun or underrun has occurred
	this bit is cleared by resetting the port via bit 2
 4	reserved
 3	enable auto-powerdown
 2	reset parallel port (pulse this bit; must remain high for 1.13 us)
 1	(read-only) parallel port is idle
 0	power-down parallel port
Note:	an explicit power-down may be canceled by either clearing bit 0 or
	  pulsing bit 2 to reset the port
SeeAlso: #P0088,#P0094

Bitfields for Intel 82091AA serial port configuration:
Bit(s)	Description	(Table P0096)
 7	enable 2MHz MIDI clock for MIDI baud rate
 6-5	reserved
 4	IRQ select
	0 = IRQ3
	1 = IRQ4
 3-1	address select
	000 PORT 03F8h-03FFh
	001 PORT 02F8h-02FFh
	010 PORT 0220h-0227h
	011 PORT 0228h-022Fh
	100 PORT 0238h-023Fh
	101 PORT 02E8h-02EFh
	110 PORT 0338h-033Fh
	111 PORT 03E8h-03EFh
 0	enable serial port
Note:	although it is possible to configure both serial ports at the same
	  address, this is not recommended because the 82091AA disables serial
	  port B without placing it into powerdown mode
SeeAlso: #P0088,#P0097

Bitfields for Intel 82091AA serial port power management register:
Bit(s)	Description	(Table P0097)
 7-5	reserved
 4	enable test mode
	when enabled, and DLAB bit in LCR is set, the baud rate clock is output
	  on the SOUTA pin
 3	enable auto-powerdown on idle
 2	reset serial port (should be pulsed, high for at least 1.13 us)
 1	(read-only) serial port is idle
 0	power-down serial port
Notes:	setting powerdown mode via bit 0 resets both receiver and transmitter,
	  including the FIFOs, so software should check that port is idle
	  before powering it down
	the serial port may be brought out of an explicit powerdown by either
	  clearing bit 0 or pulsing bit 2
SeeAlso: #P0088,#P0096

Bitfields for Intel 82091AA IDE configuration:
Bit(s)	Description	(Table P0098)
 7-3	reserved
 2	enable both primary and secondary addresses
 1	address select (when bit 2 is clear)
	0 PORT 01F0h-01F7h and 03F6h (primary)
	1 PORT 0170h-0177h and 0376h (secondary)
 0	enable IDE interface
 !!!intel\29048603.pdf p.45
SeeAlso: #P0088,#P0092

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P00220024 - PORT 0022-0024 - CHIPSET FROM PICO POWER, UMC or PCChips

PORT 0022-0024 - CHIPSET FROM PICO POWER, UMC or PCChips

0022  ?W  index for accesses to data port
0024  RW  chip set data

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P00220024 - PORT 0022-0024 - OPTi 82C281/282/283 CHIPSETS - CONFIGURATION REGISTERS

PORT 0022-0024 - OPTi 82C281/282/283 CHIPSETS - CONFIGURATION REGISTERS
Note:	every access to PORT 0024h must be preceded by a write to PORT 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  index for accesses to data port (see #P0099)
0024  RW  chip set data

(Table P0099)
Values for OPTi 82C281/82C282/82C283 configuration register index:
 10h	DRAM configuration register (see #P0100)
 11h	Shadow RAM control register (see #P0101)
 12h	Shadow RAM control register 2 (see #P0102)
 13h	Shadow RAM control register 3 (see #P0103)
 14h	miscellaneous control register (see #P0104)
 15h	cache control register (see #P0105)
 16h	cache control register 2 (see #P0106)

Bitfields for OPTi 82C281/282/283 DRAM configuration register:
Bit(s)	Description	(Table P0100)
 7-6	82C281/2 revision number (read-only)
 7	82C283 revision (0 = A, 1 = B)
 6	82C283A: reserved
	82C283B: DRAM is pipelined
 5	local DRAM read wait states
	82C281/2: 0=one, 1=two	  82C283: 0=none, 1=one
 4	local DRAM write wait states
	82C281/2: 0=one, 1=two	  82C283: 0=none, 1=one
 3-0	local DRAM memory configuration
	(val)	Bank0	Bank1	Bank2	Bank3
	0001	256K	256K	256K	256K
	0010	256K	256K	1M	-
	0011	256K	256K	1M	1M
	0100	256K	256K	4M	-
	0101	1M	-	-	-
	0110	1M	1M	-	-
	0111	1M	1M	1M	-
	1000	1M	1M	1M	1M
	1001	1M	4M	-	-
	1010	1M	1M	4M	-
	1011	4M	4M	-	-
	1100	4M	-	-	-  (82C283B only)
	1111	256K	256K	-	-
SeeAlso: #P0099

Bitfields for OPTi 82C281 shadow RAM control register:
Bit(s)	Description	(Table P0101)
 7	BIOS ROM F000-FFFF shadowing
	0 read-only from shadow RAM
	1 read from ROM, write to shadow RAM
 6	adapter ROM at E000-EFFF
	0 disable shadow RAM
	1 shadow RAM selectively enabled by configuration register 12h
	  (see #P0102)
 5	adapter ROM at D000-DFFF
	0 disable shadow RAM
	1 shadow RAM selectively enabled by configuration register 12h
 4	adapter ROM at C000-CFFF
	0 disable shadow RAM
	1 shadow RAM selectively enabled by configuration register 13h
	  (see #P0103)
 3	shadow RAM Copy Enable control (C000-EFFF)
	0 write to expansion bus
	1 write to local DRAM
 2	shadow RAM E000-EFFF writeability
	0 read/write
	1 read-only
 1	shadow RAM D000-DFFF writeability
	0 read/write
	1 read-only
 0	shadow RAM C000-CFFF writeability
	0 read/write
	1 read-only
SeeAlso: #P0099,#P0102

Bitfields for OPTi 82C281 shadow RAM control register 2:
Bit(s)	Description	(Table P0102)
 7	enable EC00-EFFF
 6	enable E800-EBFF
 5	enable E400-E7FF
 4	enable E000-E3FF
 3	enable DC00-DFFF
 2	enable D800-DBFF
 1	enable D400-D7FF
 0	enable D000-D3FF
Note:	bits 7-4 are only in effect when register 11h bit 6 is set; bits 3-0
	  are only in effect when register 11h bit 5 is set
SeeAlso: #P0099,#P0101,#P0103

Bitfields for OPTi 82C281 shadow RAM control register 3:
Bit(s)	Description	(Table P0103)
 7	enable CC00-CFFF
 6	enable C800-CBFF
 5	enable C400-C7FF
 4	enable C000-C3FF
 3-0	unused shadow RAM remap address; supplies bits 23-20 of
	  address at which to map A000-BFFFF and D000-EFFF is not used
	  for shadowing (except if this field is set to 0, the remapping
	  is disabled)
SeeAlso: #P0099,#P0101,#P0102

Bitfields for OPTi 82C281 miscellaneous control register:
Bit(s)	Description	(Table P0104)
 7	allow F0000-F0FFF to be written even while F0000-FFFFF is
	  write-protected ("Zenith mode")
 6	keyboard reset control
	=1 HLT must be executed before 82C281 generates CPU reset from
	    keyboard controller Reset command
 5	master byte swap enable
 4	82C281/2: fast NMI request
	82C283A: reserved (0)
	82C283B: ATCLK setting (=0 from register 14h bit 0; =1 CLK/8)
 3	82C281/2/3A: reserved
	82C283B: on-board DRAM parity error enable
 2	enable slow refresh mode
	(every 95.5 us (281/282) or 63.6 us (283) instead of 15.9 us)
 1	enable turbo switch function
 0	clock select
	=0 ATCLK2 = CPUCLK2 / 6
	=1 ATCLK2 = CPUCLK2 / 4
SeeAlso: #P0099

Bitfields for OPTi 82C281/82C282 cache control register:
Bit(s)	Description	(Table P0105)
 7	enable cache
 6	reserved (0)
 5	enable posted write (82C281 only)
 4	ALL accesses are non-cacheable
 3	reserved (0)
 2-0	non-cacheable region size (see also #P0106)
	000  64K
	001 128K
	...
	101  4M
	110  8M
	111 disabled
SeeAlso: #P0099,#P0106

Bitfields for OPTi 82C281/82C282 cache control register 2:
Bit(s)	Description	(Table P0106)
 7-0	starting address bits 23-16 of non-cacheable region
Note:	the specified starting address must be a multiple of the region size
SeeAlso: #P0099,#P0105

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P00220024 - PORT 0022-0024 - OPTi 82C291/82C295 CHIPSETS - CONFIGURATION REGISTERS

PORT 0022-0024 - OPTi 82C291/82C295 CHIPSETS - CONFIGURATION REGISTERS
Note:	every access to PORT 0024h must be preceded by a write to PORT 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  index for accesses to data port (see #P0107)
0024  RW  chip set data

(Table P0107)
Values for OPTi 82C291/82C295 configuration register index:
 20h	Revision/AT Bus configuration register (see #P0108)
 21h	System Control register (see #P0109)
 22h	DRAM configuration register (see #P0110)
 23h	ROM Chip Select Control register (see #P0111)
 24h	Shadow RAM control register E (see #P0112)
 25h	Shadow RAM control register D (see #P0113)
 26h	Shadow RAM control register C (see #P0114)
 27h	Shadow RAM Write Protect/Remap Area (see #P0115)
 28h	Cache Control register (see #P0116)
 29h	Cacheable Upper Bound register (see #P0117)
 2Ah	Non-Cacheable Segments register 1 (see #P0118)
 2Bh	Non-Cacheable Segments register 2 (see #P0119)
 2Ch	Non-Cacheable Segments register 3 (see #P0120)

Bitfields for OPTi 82C291/82C295 AT Bus configuration register:
Bit(s)	Description	(Table P0108)
 7-6	82C291/295 revision (read-only)
 5-4	back-to-back I/O recovery time
	00-11 = 3-6 ATCLKs between I/O accesses
 3	enable slow refresh mode
 2	enable hidden refresh
 1-0	AT clock selection
	00 ATCLK = CLK2 / 10
	01 ATCLK = CLK2 / 8
	10 ATCLK = CLK2 / 6
	11 ATCLK = CLK2 / 4
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 System Control register:
Bit(s)	Description	(Table P0109)
 7	AT bus master byte swap enabled
 6	ALE generation for each AT cycle
	0 a new ALE will be generated during bus conversion cycles
	1 multiple ALEs will be generated during bus conversion cycles
 5	keyboard fast reset emulation control
	0 enable, a "Halt" is required before a fast CPU reset is generated
	1 disable, fast CPU reset is generated directly after the "FE" I/O
	  command to port 64h is decoded
 4	AT cycle additional wait state
	0 disable, standard AT cycle
	1 enable, inserts one extra wait state in standard AT bus cycle
 3-2	reserved
 1	local device ready control
	0 RDYI# input to the 82C291 will be synchronized and set as RDY# to
	  the CPU one T-state delayed
	1 RDYI# input to the 82C291 will not be output to the CPU. RDY# from
	  the local device must be directed to the 82C291 and the CPU
 0	system memory parity checking
	0 disable, no parity checking	     
	1 enable, will check parity
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 DRAM Configuration register:
Bit(s)	Description	(Table P0110)
 7-6	number of DRAM read cycle wait states
 5-4	number of DRAM write cycle wait states
 3-0	Banks 0 thru 3 DRAM configuration
	(val)	Bank0	Bank1	Bank2	Bank3
	0000	256K	256KB	-	-
	0001	256K	256K	256K	256K
	0010	256K	256K	1M	-
	0011	256K	256K	1M	1M
	0100	256K	256K	4M	-
	0101	1M	-	-	-
	0110	1M	1M	-	-
	0111	1M	1M	1M	-
	1000	1M	1M	1M	1M
	1001	1M	4M	-	-
	1010	1M	1M	4M	-
	1011	4M	-	-	-
	1100	4M	4M	-	-
	1101	reserved
	1110	reserved
	1111	reserved
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 ROM Chip Select Control register:
Bit(s)	Description	(Table P0111)
 7	enable ROM Chip Select for write cycles (to support flash ROMs)
 6	enable ROMCS# for 0F0000-0FFFFF segments
 5	enable ROMCS# for 0E8000-0EFFFF segments
 4	enable ROMCS# for 0E0000-0E7FFF segments
 3	enable ROMCS# for 0D8000-0DFFFF segments
 2	enable ROMCS# for 0D0000-0D7FFF segments
 1	enable ROMCS# for 0C8000-0CFFFF segments
 0	enable ROMCS# for 0C0000-0C7FFF segments
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 Shadow RAM control register E:
Bit(s)	Description	(Table P0112)
 7	enable shadow RAM reads for EC000-EFFFF segments
 6	enable shadow RAM reads for E8000-EBFFF segments
 5	enable shadow RAM reads for E4000-E7FFF segments
 4	enable shadow RAM reads for E0000-E3FFF segments
 3	enable shadow RAM writes for EC000-EFFFF segments
 2	enable shadow RAM writes for E8000-EBFFF segments
 1	enable shadow RAM writes for E4000-E7FFF segments
 0	enable shadow RAM writes for E0000-E3FFF segments
Note:	OPTi documentation incorrectly states the segment range for bits 5
	  and 1 as E4000-E7000.
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 Shadow RAM control register D:
Bit(s)	Description	(Table P0113)
 7	enable shadow RAM reads for DC000-DFFFF segments
 6	enable shadow RAM reads for D8000-DBFFF segments
 5	enable shadow RAM reads for D4000-D7FFF segments
 4	enable shadow RAM reads for D0000-D3FFF segments
 3	enable shadow RAM writes for DC000-DFFFF segments
 2	enable shadow RAM writes for D8000-DBFFF segments
 1	enable shadow RAM writes for D4000-D7FFF segments
 0	enable shadow RAM writes for D0000-D3FFF segments
Note:	OPTi documentation incorrectly states the segment range for bits 5
	  and 1 as D4000-D7000.
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 Shadow RAM control register C:
Bit(s)	Description	(Table P0114)
 7	enable shadow RAM reads for CC000-CFFFF segments
 6	enable shadow RAM reads for C8000-CBFFF segments
 5	enable shadow RAM reads for C4000-C7FFF segments
 4	enable shadow RAM reads for C0000-C3FFF segments
 3	enable shadow RAM writes for CC000-CFFFF segments
 2	enable shadow RAM writes for C8000-CBFFF segments
 1	enable shadow RAM writes for C4000-C7FFF segments
 0	enable shadow RAM writes for C0000-C3FFF segments
Note:	OPTi documentation incorrectly states the segment range for bits 5
	  and 1 as C4000-C7000.
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 Shadow RAM Write Protect/Remap Area:
Bit(s)	Description	(Table P0115)
 7	enable Write Protect for F0000-FFFFF segments
 6	enable Write Protect for E0000-EFFFF segments
 5	enable Write Protect for D0000-DFFFF segments
 4	enable Write Protect for C0000-CFFFF segments
 3-0	DRAM remap starting address, bits 23-20
	0000  disabled, no mapping
	0001  1M
	0010  2M
	...
	1111 15M
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 Cache Control register:
Bit(s)	Description	(Table P0116)
 7	enable write-back cache controller operation
 6	enable DRAM performance mode
	this bit should not be enabled unless external cache is disabled
	  (intended to optimize DRAM performance)
 5	enable all memory accesses no-cacheable mode
 4	enable 640K-1M area no-cacheable mode
 3-2	cache timing control bits
	00 invalid
	01 0 wait state cache write w/o CAWE# extended, use when 8K*8 SRAMs
	10 1 wait state cache write hit
	11 0 wait state cache write hit with CAWE# extended when 32K*8 SRAMs
 1-0	cache size/cacheable DRAM
	00  16K /  2M
	01  32K /  4M
	10  64K /  8M
	11 128K / 16M
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 Cacheable Upper Bound register:
Bit(s)	Description	(Table P0117)
 7-4	reserved
 3-0	cacheable upper bound address, bits 23-20
	0000  feature disabled
	0001  1M
	0010  2M
	...
	1111 15M
SeeAlso: #P0107

Bitfields for OPTi 82C291/82C295 Non-Cacheable Segments register 1:
Bit(s)	Description	(Table P0118)
 7	enable non-cacheable segment A
 6-4	size of no-cacheable memory segment A
	000  64K
	001 128K
	010 256K
	011 512K
	100   1M
	101   2M
	110   4M
	111   8M
 3	enable non-cacheable segment B
 2-0	size of no-cacheable memory segment B (same values as bits 6-4)
SeeAlso: #P0107,#P0119
    
Bitfields for OPTi 82C291/82C295 Non-Cacheable Segments register 2:
Bit(s)	Description	(Table P0119)
 7-0	address bits 23-16 for starting address of non-cacheable memory
	  segment A
SeeAlso: #P0107,#P0118,#P0120

Bitfields for OPTi 82C291/82C295 Non-Cacheable Segments register 3:
Bit(s)	Description	(Table P0120)
 7-0	address bits 23-16 for starting address of non-cacheable memory
	  segment B
SeeAlso: #P0107,#P0118,#P0119

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P00220024 - PORT 0022-0024 - OPTi 82C381/82C382 CHIPSETS - CONFIGURATION REGISTERS

PORT 0022-0024 - OPTi 82C381/82C382 CHIPSETS - CONFIGURATION REGISTERS
Note:	every access to PORT 0024h must be preceded by a write to PORT 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  index for accesses to data port (see #P0121)
0024  RW  chip set data

(Table P0121)
Values for OPTi 82C381/82C382 configuration register index:
 00h	clock selects (see #P0122)
 01h	reset control (see #P0123)
 10h	remapping address (see #P0124)
 11h	shadow RAM (see #P0125)
 12h	memory enable (see #P0126)
 13h	bank configuration (see #P0127)
 14h	DRAM configuration (see #P0128)
 15h	video adapter shadow (see #P0129)
 16h	fast GateA20 (see #P0130)
 17h	cache configuration (see #P0131)
 18h	non-cacheable block 1 size (see #P0132)
 19h	non-cacheable block 1 address (see #P0133)
 1Ah	non-cacheable block 2 size (see #P0132)
 1Bh	non-cacheable block 2 address (see #P0133)
 1Ch	cacheable area (see #P0134)
Note:	registers 00h and 01h address the 82C381, the remaining registers
	  address the 82C382
SeeAlso: #P0189

Bitfields for OPTi 82C381/82C382 clock selects:
Bit(s)	Description	(Table P0122)
 7-6	cache controller enable
	00 cache controller disabled (default)
	01 cache controller disabled; PPCS#, SPCS#, NPCS# signals are
	      active if selected
	10 external cache controller installed
	11 on-chip cache controller installed
 5	hot CPU reset (low->high transition generates reset)
 4	enable ATCLK stretch
 3	turbo clock
	=0 CLKIN is CPU clock
	=1 HIGH pin selected clock (HIGH=0: CLKIN, HIGH=1: ICLK)
 2-1	ICLK clock select
	00 CLKIN/4 (default)
	01 CLKIN/3
	10 CLKIN/2
	11 reserved
 0	master byte swap enable (default = 0)
SeeAlso: #P0121,#P0123

Bitfields for OPTi 82C381/82C382 reset control:
Bit(s)	Description	(Table P0123)
 7-2	reserved
 1	RESET3 control
	=1 generate RESET3 on RESET2 only after a HLT instruction
	=0 generate RESET3 immediately on RESET2 (default)
 0	activate cache controller FLUSH# pin (default = 1)
SeeAlso: #P0121,#P0122,#P0124

Bitfields for OPTi 82C381/82C382 remapping address:
Bit(s)	Description	(Table P0124)
 7-5	reserved
 4	enable remapping
 3-0	remap address range, bits 23-20
	0000  no mapping
	0001  1M
	0010  2M
	...
	1111 15M
SeeAlso: #P0121

Bitfields for OPTi 82C381/82C382 shadow RAM control:
Bit(s)	Description	(Table P0125)
 7	BIOS ROM at F0000-FFFFF Shadowing
	0 read only from shadow RAM
	1 read from ROM, write to shadow RAM
 6	ROM at D0000-DFFFF
	0 disable shadow RAM
	1 shadow RAM selectively enabled by configuration register 12h
 5	Adaptor ROM at E0000-EFFFF
	0 disable shadow RAM
	1 shadow RAM selectively enabled by configuration register 12h
 4	write-protect shadow RAM at D0000h-DFFFFh (default = not protected)
 3	write-protect shadow RAM at E0000h-EFFFFh
 2	enable Timeout precharge counter 
 1-0	reserved
SeeAlso: #P0121

Bitfields for OPTi 82C381/82C382 memory enable:
Bit(s)	Description	(Table P0126)
 7	enable EC000-EFFFF
 6	enable E8000-EBFFF
 5	enable E4000-E7FFF
 4	enable E0000-E3FFF
 3	enable DC000-DFFFF
 2	enable D8000-DBFFF
 1	enable D4000-D7FFF
 0	enable D0000-D3FFF
Note:	0 = disable Shadow RAM (default), 1 = enable Shadow RAM
SeeAlso: #P0121

Bitfields for OPTi 82C381/82C382 memory bank configuration:
Bit(s)	Description	(Table P0127)
 7	Reserved
 6-4	Bank0 and Bank1 configuration
	(val)	Bank0	 Bank1 
	000	256K	 -  
	001	256K	 256K
	010	256K	 1M  
	011	1M	 256K
	100	1M	 -  
	101	1M	 1M 
	110	-	 -  
	111	256K	 - 
 3	reserved
 2-0	Bank2 and Bank3 configuration
	(val)	Bank2	 Bank3 
	000	256K	 -  
	001	256K	 256K
	010	-	 -  
	011	1M	 256K
	100	1M	 -  
	101	1M	 1M 
	11X	-	 -  
SeeAlso: #P0121,#P0128

Bitfields for OPTi 82C381/82C382 DRAM configuration:
Bit(s)	Description	(Table P0128)
 7,6	number of read cycle wait states (default = 01)
 5	write cycle wait state
	0 = 0 wait 
	1 = 1 wait (default)	  
 4-0	reserved	
SeeAlso: #P0121

Bitfields for OPTi 82C381/82C382 video adapter shadow:
Bit(s)	Description	(Table P0129)
 7	reserved
 6	copy enable for C0000-EFFFF
	0 write to AT Channel (default) 
	1 write to local DRAM
 5	Shadow RAM at C0000-CFFFF writability
	0 read/write (default)
	1 read only
 4	ROM at C0000-CFFFF
	0 disable shadow RAM
	1 shadow RAM selectively enabled by Bits<0:3> (default)
 3	enable Shadow RAM at CC000-CFFFF
 2	enable Shadow RAM at C8000-CbFFF
 1	enable Shadow RAM at C4000-C7FFF
 0	enable Shadow RAM at C0000-C3FFF
SeeAlso: #P0121

Bitfields for OPTi 82C381/82C382 fast GateA20 control:
Bit(s)	Description	(Table P0130)
 7-4	Reserved
 3	Fast GateA20 Control  
	0 Signal controled by GATEA20 signal from Keyboard Controler
	1 CPUA20 enabled onto GA20
 2-0	reserved	
SeeAlso: #P0121

Bitfields for OPTi 82C381/82C382 cache configuration:
Bit(s)	Description	(Table P0131)
 7	force NCA* Output Pin low
	if this bit is clear, it has no effect on NCA* Output Pin
 6	enable Cache
 5	write-through cache (Note: this bit must be set)
 4-3	line size
	00  4 bytes 
	01  8 bytes
	10  16 bytes
	11  reserved
 2-0	reserved	
SeeAlso: #P0121

Bitfields for OPTi 82C381/82C382 non-cacheable block size:
Bit(s)	Description	(Table P0132)
 7-5	block size
	000 64K
	001 128K
	010 256K
	011 512K
	100 1M
	101 4M (block 1 only)
	101 reserved (block 2 only)
	110 8M (block 1 only)
	110 reserved (block 2 only)
	111 disabled (default)
 4-0	reserved (0)
SeeAlso: #P0121,#P0131,#P0133

Bitfields for OPTi 82C381/82C382 non-cacheable block address:
Bit(s)	Description	(Table P0133)
 7-0	bits 23-16 of non-cacheable block's address
Note:	the selected address must be a multiple of the block size
	  selected by register 18h/1Ah
SeeAlso: #P0121,#P0132,#P0134

Bitfields for OPTi 82C381/82C382 cacheable area:
Bit(s)	Description	(Table P0134)
 7-4	cacheable address range
	0000 16M
	0001 1M
	0010 2M
	0011 3M
	...
	1111 15M
 3	256K remapped area is cacheable
 2-0	reserved
SeeAlso: #P0121

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P00220024 - PORT 0022-0024 - OPTi 82C463MV CHIPSET - CONFIGURATION REGISTERS

PORT 0022-0024 - OPTi 82C463MV CHIPSET - CONFIGURATION REGISTERS
Desc:	the 82C463MV contains a memory control unit (MCU), an AT Bus
	  Control Unit (BCU), a Power Management Unit (PMU), data
	  buffers and a 82C206 type IPC (without real time clock)
Note:	every access to PORT 0024h must be preceded by a write to PORT 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  index for accesses to data port (see #P0135)
0024  RW  chip set data

(Table P0135)
Values for OPTi 82C463MV configuration register index:
 30h	general control 1 (see #P0136)
 31h	general control 2 (see #P0137)
 32h	shadow RAM control 1 (see #P0138)
 33h	shadow RAM control 2 (see #P0139)
 34h	DRAM size (see #P0140)
 35h	DRAM timing and caching control (see #P0141)
 36h	shadow RAM control 3 (see #P0142)
 37h	D000h and E000h segment access control (see #P0143)
 38h	non-cacheable block 1 size, controls and address bit A24 (see #P0144)
 39h	non-cacheable block 1 address bits A23-A16
 3Ah	non-cacheable block 2 size and address bit A24 (see #P0145)
 3Bh	non-cacheable block 2 address bits A23-A16
 3Ch-3Fh	reserved
 40h	PMU control 1 (see #P0146)
 41h	PMU control 2: doze timer (see #P0147)
 42h	PMU control 3: other timers (see #P0148)
 43h	PMU control 4 (see #P0149)
 44h	LCD timer count (should not be loaded with a value <5)
 45h	disk timer count (should not be loaded with a value <5)
 46h	keyboard timer count (should not be loaded with a value <5)
 47h	GNR_ACCESS timer count (should not be loaded with a value <5)
 48h	GNR_ACCESS I/O base address (lines A8-A1, A0 is a "don't care")
 49h	GNR_ACCESS control and I/O base address line A9 (see #P0150)
 4Ah	CSG0# base address (lines A8-A1, A0 is a "don't care")
 4Bh	CSG0# control and base address line A9 (see #P0151)
 4Ch	CSG1# base address (lines A8-A1, A0 is a "don't care")
 4Dh	CSG1# control and base address line A9 (see #P0152)
 4Eh	idle timer control (see #P0153)
 4Fh	idle timer count (should not be loaded with a value <5)
 50h	suspend/resume control (see #P0154)
 51h	beeper/sequencer control (see #P0155)
 52h	PMU general-purpose storage 1
 53h	PMU general-purpose storage 2
 54h	PMU Periferal Power (PPWR) control 1 (see #P0156)
 55h	PMU Periferal Power (PPWR) control 2 (see #P0157)
 56h	PIO control 1 (see #P0158)
 57h	PIO control 2 (see #P0159)
 58h	PMU event control 1 (see #P0160)
 59h	PMU event control 2 (see #P0161)
 5Ah	PMU event control 3 (see #P0162)
 5Bh	PMU event control 4 (see #P0163)
 5Ch	SMI source (low) (see #P0164)
 5Dh	SMI source (high) (see #P0165)
 5Eh	clock stretching control (see #P0166)
 5Fh	resume interrupt control (see #P0167)
 60h	software sequencer address (write only)
 61h	debounce control (see #P0168)
 62h	doze-mode IRQ selects (see #P0169)
 63h	idle timer IRQ selects (see #P0170)
 64h	PMI#6 IRQ select (see #P0171)
 65h	doze-mode configuration (see #P0172)
 66h	suspend control (see #P0173)
 67h	CPU frequency (see #P0174)
 68h	timer clock source (see #P0175)
 69h	R_TIMER count (should not be loaded with a value <5)
 6Ah	resume IRQ selects (see #P0176)
 6Bh	resume sources (see #P0177)
 6Ch-6Fh	TMP0 - TMP3

Bitfields for 82C463MV general control 1 (register 30h):
Bit(s)	Description	(Table P0136)
 7-6	chipset revision number (read only)
 5	MASTER#/RI pin function (RI = modem Ring Indicator)
	=1 RI (default)
	=0 MASTER#
 4	enable turbo VGA
 3	enable global relocation/translation for SMI addresses (see also
	  register 31h bit 4 at #P0137)
 2	enable extra wait state in AT cycle
 1	fast reset control
	  =1 does not require Halt instruction
	  =0 requires Halt instruction before generation of CPURST (SRESET
	       if Intel SL Enhanced or Cyrix Cx486S/S2 CPUs
 0	reserved (0)
SeeAlso: #P0135

Bitfields for 82C463MV general control 2 (register 31h):
Bit(s)	Description	(Table P0137)
 7	enable master byte swap
 6	reserved, read-only (1)
 5	disable parity check
 4	Dynamic SMI relocation
	  if no SMI sequence is running
	    =1 allow relocation of addresses from the CPU in the 3000h/4000h
	       segment to the B000h/A000h SMI memory space
	    =0 disable relocation
	  if SMI sequence is running (qualified by SMIACT#)
	    =1 allow data accesses to the 3000h and 4000h segments
	    =0 relocate all accesses in the 3000h/4000h segment to the
	       B000h/A000h SMI segment (normal operation)
	  if SMI sequence is running (qualified by SMIADS#)
	    =1 not allowed
	    =0 for a SMIADS# cycle, relocate all accesses in the 6000h/7000h
	       segment to the A000h/B000h SMI segment
	       for a normal ADS# operation, there is no relocation
 3	EC000h-EFFFFh access control
	if register 36h bit 6=0
	  =1 R/W from ROMCS#
	  =0 R/W from AT-Bus
	if register 36h bit 6=1
	  =1 Read from ROMCS# if not shadowed (see register 33h bits 7-4),
		write to DRAM
	  =0 Read from AT-Bus if not shadowed (see register 33h bits 7-4),
		write to DRAM
 2	E8000h-EBFFFh access control (see bit 3)
 1	E4000h-E7FFFh access control (see bit 3)
 0	E0000h-E3FFFh access control (see bit 3)
SeeAlso: #P0135,#P0139,#P0142

Bitfields for 82C463MV shadow RAM control 1 (register 32h):
Bit(s)	Description	(Table P0138)
 7	segment F000h access control
	  =1 read from ROMCS#, write to ROMCS# (if register 36h bit 7=1)
	     or DRAM (if register 36h bit 7=0)
	  =0 read from DRAM and write protect (enable shadowing)
 6-5	reserved (1)
 4	write protect segment D000h
 3	write protect segment E000h
 2	reserved, read-only (1)
 1	reserved (0)
 0	ALE control
	  =1 single ALE during bus conversion
	  =0 multiple ALE
SeeAlso: #P0135,#P0142,#P0139

Bitfields for 82C463MV shadow RAM control 2 (register 33h):
Bit(s)	Description	(Table P0139)
 7	enable shadowing for EC000h-EFFFFh
 6	enable shadowing for E8000h-EBFFFh
 5	enable shadowing for E4000h-E7FFFh
 4	enable shadowing for E0000h-E3FFFh
 3	enable shadowing for DC000h-DFFFFh
 2	enable shadowing for D8000h-DBFFFh
 1	enable shadowing for D4000h-D7FFFh
 0	enable shadowing for D0000h-D3FFFh
SeeAlso: #P0135,#P0138

Bitfields for 82C463MV DRAM size (register 34h):
Bit(s)	Description	(Table P0140)
 7-4	DRAM Bank 0 and 1 Size
	0000 256K, unused
	0001 256K, 256K
	0010 256K, 1M
	0011 256K, 4M
	0100 512K, unused
	0101 512K, 512K
	0110 512K, 1M
	0111 512K, 4M
	1000 1M, unused
	1001 1M, 1M
	1010 1M, 4M
	1011 4M, 1M
	1100 4M, unused
	1101 4M, 4M
	1110 1M, 2M
	1111 both unused
 3-0	DRAM Bank 2 and 3 Size
	0000 1M, unused
	0001 1M, 1M
	0010 1M, 4M
	0011 4M, 4M
	0100 4M, unused
	0101 both unused
	0110 1M, 2M
	0111 512K, 512K
	10xx both unused
	110x both unused
	1110 2M, unused
	1111 2M, 2M (default)
SeeAlso: #P0135

Bitfields for 82C463MV DRAM timing and caching control (register 35h):
Bit(s)	Description	(Table P0141)
 7-6	DRAM read wait states
	00 = 0 wait states, burst mode 2-1-1-1
	01 = 1 wait state, burst mode 3-1-1-1
	10 = 1 wait state, burst mode 3-2-2-2
	11 = 2 wait states, burst mode 4-3-3-3 (default)
 5-4	DRAM write wait states
	00 = 0 wait states
	01 = 1 wait state
	10 = 2 wait states
	11 = reserved (default)
 3	MP2/STRAP2 status (read-only)
	=1 1X Clock
	=0 2X Clock
 2	disable caching of F000h segment (this bit is effective only when
	  register 32h bit 7 =0)
 1	global DRAM cache control (1=disable, default)
 0	disable caching of C0000h-C7FFFh (default)
SeeAlso: #P0135,#P0138

Bitfields for 82C463MV shadow RAM control 3 (register 36h):
Bit	Description	(Table P0142)
 7	segment F000h write control
	=1 write to ROMCS#
	=0 write to DRAM
	don't care if register 32h bit 7=0
 6	C0000h-EFFFFh control
	=1 read from AT-Bus or ROMCS# (if ROMCS# is enabled to that block),
	  write to DRAM
	=0 R/W from AT bus or ROMCS# (if ROMCS# is enabled to that block)
 5	write protect segment C000h
 4	reserved (1)
 3	enable shadowing for CC000h-CFFFFh
 2	enable shadowing for C8000h-CBFFFh
 1	enable shadowing for C4000h-C7FFFh
 0	enable shadowing for C0000h-C3FFFh
SeeAlso: #P0135,#P0138

Bitfields for 82C463MV D000h and E000h segments access control (register 37h):
Bit	Description	(Table P0143)
 7	DC000h-DFFFFh access control
	if register 36h bit 6=1
	    =1 read from ROMCS# if not shadowed, write to DRAM
	    =0 read from AT-Bus if not shadowed, write to DRAM
	if register 36h bit 6=0
	    =1 R/W from ROMCS#
	    =0 R/W from AT-Bus
 6	D8000h-DBFFFh access control (see bit 7)
 5	D4000h-D7FFFh access control (see bit 7)
 4	D0000h-D3FFFh access control (see bit 7)
 3	disable caching for EC000h-EFFFFh (default)
 2	disable caching for E8000h-EBFFFh (default)
 1	disable caching for E4000h-E7FFFh (default)
 0	disable caching for E0000h-E3FFFh (default)
SeeAlso: #P0135,#P0142

Bitfields for non-cacheable block 1 size, control and A24 (register 38h):
Bit(s)	Description	(Table P0144)
 7-5	size of non-cacheable memory block 1
	000 64K
	001 128K
	010 256K
	011 1M
	1xx disabled (default)
 4	CC000h-CFFFFh access control
	if register 36h bit 6=1
	    =1 read from ROMCS# if not shadowed, write to DRAM
	    =0 read from AT-Bus if not shadowed, write to DRAM
	if register 36h bit 6=0
	    =1 R/W from ROMCS#
	    =0 R/W from AT-Bus
 3	C8000h-CBFFFh access control (see bit 4)
 2	C4000h-C7FFFh access control (see bit 4)
 1	C0000h-C3FFFh access control (see bit 4)
 0	address bit A24 of non-cacheable memory block 1
SeeAlso: #P0135,#P0142

Bitfields for non-cacheable block 2 size and A24 (register 3Ah):
Bit(s)	Description	(Table P0145)
 7-5	size of non-cacheable memory block 2
	000 64K
	001 128K
	010 256K
	011 1M
	1xx disabled (default)
 4	unused
 3	enable internal HLDA latch during stop clock (must be disabled
	  before DMA transfers are performed)
 2	reserved (1)
 1	unused
 0	address bit A24 of non-cacheable memory block 2
SeeAlso: #P0135

Bitfields for 82C463MV PMU control 1 (register 40h):
Bit	Description	(Table P0146)
 7	Reset/SMI indication (read-only)
	=1 the last read or fetch from address XXXFFFF0h was a SMIADS#
	     cycle
	=0 the last read or fetch from address XXXFFFF0h was a regular
	     ADS# cycle
 6	divide global timer by 4
 5	LLOWBAT polarity selector
	=1 low active
	=0 high active
 4	LOWBAT polarity selector (see bit 5)
 3	SQWIN input clock frequency
	=1 128KHz
	=0 32KHz
 2	external EPMI2 pin polarity
	=1 active low
	=0 active high
 1	external EPMI1 pin polarity (see bit 2)
 0	send reset pulse during resume
Note:	for 1X clock with Intel SL Enhanced CPU, bit 6 must be =1
SeeAlso: #P0135,#P0147,#P0148

Bitfields for 82C463MV PMU control 2 (doze timer, register 41h):
Bit(s)	Description	(Table P0147)
 7-5	hardware doze time-out selector
	101 512 ms
	110 2 sec
	111 8 sec
 4-2	hardware doze-mode CPU clock selector
	000 CPUCLK/1
	001 CPUCLK/2
	010 CPUCLK/4
	011 CPUCLK/8 (should be used during CPU stop clock only)
	100 CPUCLK/16 (should be used during CPU stop clock only)
	101 CPUCLK/3
	110 reserved
	111 reserved
 1	enable LCD_ACCESS, KBD_ACCESS, DSK_ACCESS access to auto trigger
	  the hardware doze timer
 0	disable hardware doze-mode (enable APM doze-mode support)
SeeAlso: #P0135,#P0146,#P0148

Bitfields for 82C463MV PMU control 3 (timers other than doze, register 42h):
Bit(s)	Description	(Table P0148)
 7-6	clock source for general-purpose timer
	00 SQW0
	01 SQW1
	10 SQW2
	11 SQW3
 5-4	clock source for keyboard timer (see bits 7-6)
 3-2	clock source for disk timer (see bits 7-6)
 1-0	clock source for LCD timer (see bits 7-6)
SeeAlso: #P0135,#P0147,#P0149

Bitfields for 82C463MV PMU control 4 (register 43h):
Bit(s)	Description	(Table P0149)
 7	disable monitoring of PORT 3B0h-3DFh
 6	disable monitoring of memory range A0000h-BFFFFh
 5-4	LOWBAT pin sample rate
	if register 40h bit 6 =1
	    00 32 seconds
	    01 64 seconds
	    10 128 seconds
	    11 reserved
	if register 40h bit 6	 =0
	    00 8 seconds
	    01 16 seconds
	    10 32 seconds
	    11 reserved
 3	reserved (0)
 2-0	AT clock select
	000 OSCCLK2/8
	001 OSCCLK2/6
	010 OSCCLK2/4
	011 OSCCLK2/3
	100 OSC14/2 (7.2 MHz)
	111 stop
SeeAlso: #P0135,#P0146,#P0149,#P0150

Bitfields for 82C463MV GNR_ACCESS control, I/O base address line A9 (reg. 49h):
Bit(s)	Description	(Table P0150)
 7	GNR_ACCESS I/O base address bit A9
 6	enable compare in WRITE cycle
 5	enable compare in READ cycle
 4-0	I/O address A5-A1 mask bits. For each bit =1, the corresponding bit
	  in register 48h is not compared (this is used to determine I/O
	  address block size)
SeeAlso: #P0135,#P0149

Bitfields for 82C463MV CSG0# control and base address line A9 (register 4Bh):
Bit(s)	Description	(Table P0151)
 7	Programmable Chip Select 0 (CSG0#) - I/O base address line A9
 6	enable CSG0# for I/O write cycles
 5	enable CSG0# for I/O read cycles
 4	=1 CSG0# active before ALE
	=0 CSG0# active just like I/O command pulse
 3-0	I/O address A4-A1 mask bits. For each bit =1, the corresponding bit
	  in register 4Ah (bits 4-1) is not compared (this is used to
	  determine I/O address block size)
SeeAlso: #P0135,#P0152

Bitfields for 82C463MV CSG1# control and base address line A9 (register 4Dh):
Bit(s)	Description	(Table P0152)
 7	Programmable Chip Select 1 (CSG1#) - I/O base address line A9
 6	enable CSG1# for I/O write cycles
 5	enable CSG1# for I/O read cycles
 4	=1 CSG1# active before ALE
	=0 CSG1# active just like I/O command pulse
 3-0	I/O address A4-A1 mask bits. For each bit =1, the corresponding bit
	in register 4Ch (bits 4-1) is not compared (this is used to
	determine I/O address block size)
SeeAlso: #P0135,#P0151

Bitfields for OPTi 82C463MV idle timer control (register 4Eh):
Bit	Description	(Table P0153)
 7	CSG1 access
 6	CSG0 access
 5	LPT access (it refers to PORT 378h-37Fh, PORT 278h-27Fh and
	  PORT 3BCh-3BFh)
 4	COM access (it refers to PORT 3F8h-3FFh and PORT 2F8h-2FFh)
 3	GNR_ACCESS
 2	KBD_ACCESS
 1	DSK_ACCESS
 0	LCD_ACCESS
Note:	If a bit is =1, the corresponding access will reload IDLE_TIMER
	  otherwise not.
SeeAlso: #P0135

Bitfields for 82C463MV suspend/resume control (register 50h):
Bit	Description	(Table P0154)
 7	software generation of SMI (enabled by bit 7 of register 59h)
	  writing 1 asserts SMI to CPU to start SMM operation
	  writing 0 clears the SMI (the SMI routine must clear this bit)
 6	reserved (0)
 5	IRQ8 active level
	=1 high active
	=0 low active
 4	disable the internal 14.3MHz clock (to conserve power)
 3	start doze-mode / read DOZE_TIMER status
	write: start APM doze-mode
	    =1 start doze-mode (if register 40h bit 0 =1)
	    =0 no effect
	read: hardware DOZE_TIMER time-out status bit
	    =1 hardware DOZE_TIMER has timed out
	    =0 hardware DOZE_TIMER still counting
 2	Ready To Resume (RTR), read-only
 1	PMU mode (read-only)
	=1 suspend-mode still active
	=0 all other modes
 0	start suspend-mode (write only)
	=1 start suspend-mode
	=0 no effect
SeeAlso: #P0135,#P0146,#P0161

Bitfields for 82C463MV beeper/sequencer control (register 51h):
Bit(s)	Description	(Table P0155)
 7-2	sequencer base address translated-to A17-A12 (A19-A18 are always 1
	  during this operation)
 1-0	beeper control (independent from PORT 61h)
	if register 40h bit 6 =1
	    00 no action
	    01 1KHz
	    10 off
	    11 2KHz
	if register 40h bit 6 =0
	    00 no action
	    01 4KHz
	    10 off
	    11 8KHz
SeeAlso: #P0135,#P0146

Bitfields for 82C463MV PMU Periferal Power (PPWR) control 1 (register 54h):
Bit(s)	Description	(Table P0156)
 7-4	write mask of PPWR low nibble
	=1 enable write on corresponding bit
	=0 write disable
 3-0	read/write data bits for PPWR (low nibble)
SeeAlso: #P0135,#P0157

Bitfields for 82C463MV PMU Periferal Power (PPWR) control 2 (register 55h):
Bit(s)	Description	(Table P0157)
 7-4	write mask of PPWR high nibble
	=1 enable write on corresponding bit
	=0 write disable
 3-0	read/write data bits for PPWR (high nibble) (default =1)
SeeAlso: #P0135,#P0156

Bitfields for OPTi 82C463MV PIO control 1 (register 56h):
Bit(s)	Description	(Table P0158)
 7-4	write mask of PIO bits 3-0
	=1 enable write on corresponding bit
	=0 write disable
 3-0	read/write data bits for PIO
SeeAlso: #P0135,#P0159,#P0173

Bitfields for OPTi 82C463MV PIO control 2 (register 57h):
Bit	Description	(Table P0159)
 7	enable refresh (BIOS must set this bit to 1 after power up)
 6	enable interrupts to generate PMI #6 (see also #P0167,#P0171)
 5	disable monitoring floppy drive accesses
 4	disable monitoring hard drive accesses
 3	PIO3/STPGNT# pin direction
	=1 output
	=0 input
 2	PIO2/CPUSPD pin direction (see bit 3)
 1	PIO1/NOWS# pin direction (see bit 3)
 0	PIO0 pin direction (see bit 3)
SeeAlso: #P0135,#P0158

Bitfields for OPTi 82C463MV PMU event control 1 (register 58h):
Bit(s)	Description	(Table P0160)
 7-6	LOWBAT PMI #3 configuration
	00 disable
	01 sequencer
	10 reserved
	11 SMI
 5-4	EPMI2 PMI #2 configuration (see bits 7-6)
 3-2	EPMI1 PMI #1 configuration (see bits 7-6)
 1-0	LLOWBAT PMI #0 configuration (see bits 7-6)
SeeAlso: #P0135

Bitfields for OPTi 82C463MV PMU event control 2 (register 59h):
Bit(s)	Description	(Table P0161)
 7	global software SMI enable (see also bit 7 of register 50h at #P0154)
 6	reload timers during a resume sequence
 5-4	resume or INTR PMI #6 and Suspend PMI #7 configuration
	00 disable
	01 sequencer
	10 reserved
	11 SMI
 3-2	R_TIMER PMI #5 configuration (see bits 5-4)
 1-0	IDLE_TIMER PMI #4 configuration (see bits 5-4)
SeeAlso: #P0135

Bitfields for OPTi 82C463MV PMU event control 3 (register 5Ah):
Bit(s)	Description	(Table P0162)
 7-6	GNR_TIMER time out PMI #11 and access PMI #15 configuration
	00 disable
	01 sequencer
	10 reserved
	11 SMI
 5-4	KBD_TIMER time out PMI #10 and access PMI #14 cfg (see bits 7-6)
 3-2	DSK_TIMER time out PMI #9 and access PMI #13 cfg (see bits 7-6)
 1-0	LCD_TIMER time out PMI #8 and access PMI #12 cfg (see bits 7-6)
SeeAlso: #P0135,#P0163

Bitfields for OPTi 82C463MV PMU event control 4 (register 5Bh):
Bit	Description	(Table P0163)
 7	IRQ15 SMI select
	=1 enable SMI select (SMI internally connected to IRQ15) and
	  disable IRQ15 hardware pin function
	=0 disable SMI select (enable IRQ15 pin function as normal)
 6	disable all SMI
 5	enable sequencer
 4	SMI Type
	=0 Intel style SMI (SMM identified by SMIACT#)
	=1 AMD DXLV or Cyrix style SMI (SMM identified by SMIADS#)
	Note:	for Intel-style SMI, the 3000h/4000h segments will relocate to
		  B000h/A000h when in SMM; for AMD/Cyrix, the 7000h/6000h
		  segments will relocate to B000h/A000h when in SMM
 3	enable PMI source #15
 2	enable PMI source #14
 1	enable PMI source #13
 0	enable PMI source #12
SeeAlso: #P0135,#P0162,#P0164

Bitfields for OPTi 82C463MV SMI source (low) (register 5Ch):
Bit	Description	(Table P0164)
 7	PMI #7 - SUSPEND
 6	PMI #6 - RESUME or INTR
 5	PMI #5 - R_TIMER time out
 4	PMI #4 - IDLE_TIMER time out
 3	PMI #3 - LOWBAT pin
 2	PMI #2 - EPMI2 pin (external PMI source)
 1	PMI #1 - EPMI1 pin (external PMI source)
 0	PMI #0 - LLOWBAT pin
SeeAlso: #P0135,#P0165

Bitfields for OPTi 82C463MV SMI source (high) (register 5Dh):
Bit	Description	(Table P0165)
 7	PMI #15 - GNR_ACCESS
 6	PMI #14 - KBD_ACCESS
 5	PMI #13 - DSK_ACCESS
 4	PMI #12 - LCD_ACCESS
 3	PMI #11 - GNR_TIMER
 2	PMI #10 - KBD_TIMER
 1	PMI #9 - DSK_TIMER
 0	PMI #8 - LCD_TIMER
SeeAlso: #P0135,#P0164

Bitfields for OPTi 82C463MV clock stretching control (register 5Eh):
Bit	Description	(Table P0166)
 7	enable CPU clock stretch memory code cycle
 6	enable CPU clock stretch write cycle
 5	enable CPU clock stretch read cycle
 4	enable CPU clock stretch I/O cycle
 3	enable CPU clock stretch memory data cycle
 2	enable stop ATCLK when not in AT bus cycle
 1	ATCLK stretch
	=1 synchronous
	=0 asynchronous
 0	reserved (0)
SeeAlso: #P0135

Bitfields for OPTi 82C463MV resume interrupt control (register 5Fh):
Bit(s)	Description	(Table P0167)
 7	LCD_ACCESS includes AT bus video access
 6	LCD_ACCESS includes Local bus video access
 5	enable all resume sources of register 6Ah (see also #P0176,#P0159)
 4	RI counter count out will generate resume
 3-0	number of RI counts
SeeAlso: #P0135

Bitfields for OPTi 82C463MV debounce control (register 61h):
Bit(s)	Description	(Table P0168)
 7-6	LOWBAT and LLOWBAT pin debounce rate select
	if register 40h bit 6 =1
	    00 no debounce
	    01 250 microseconds
	    10 8ms
	    11 500ms
	if register 40h bit 6 =0
	    00 no debounce
	    01 62.5 microseconds
	    10 2 ms
	    11 125 ms
 5-4	SUSP/RSM pin debounce rate select
	if register 40h bit 6 =1
	    00 reserved
	    01 latch high to low edge
	    10 4 ms (low to high)
	    11 8 ms (low to high)
	if register 40h bit 6 =0
	    00 reserved
	    01 latch high to low edge
	    10 1 ms (low to high)
	    11 2 ms (low to high)
 3	reserved (0)
 2	enable STPCLK protocol for switching CPU clock frequencies
 1-0	STPCLK# delay (for use when STPCLK protocol is enabled)
	00 no delay
	01 120 microseconds
	10 240 microseconds
	11 1ms, if register 40h bit 6 set; 240 microseconds if clear
SeeAlso: #P0135,#P0146

Bitfields for OPTi 82C463MV doze-mode IRQ selects (register 62h):
Bit	Description	(Table P0169)
 7	enable IRQ13
 6	enable IRQ8
 5	enable IRQ7
 4	enable IRQ12
 3	enable IRQ5
 2	enable IRQ4
 1	enable IRQ3
 0	enable IRQ0
Notes:	in hardware doze-mode the selected interrupts will be used to re-load
	  the hardware DOZE_TIMER and/or trigger the system out of doze-mode
	in APM doze-mode the selected interrupts will be used to trigger the
	  system out of doze-mode only
SeeAlso: #P0135,#P0172,#P0170

Bitfields for OPTi 82C463MV idle timer IRQ selects (register 63h):
Bit	Description	(Table P0170)
 7	enable EPMI1 (level trigger)
 6	enable IRQ13
 5	enable IRQ8
 4	enable IRQ7
 3	enable IRQ5
 2	enable IRQ4
 1	enable IRQ3
 0	enable IRQ0
SeeAlso: #P0135,#P0169,#P0171

Bitfields for OPTi 82C463MV PMI#6 IRQ selects (register 64h):
Bit	Description	(Table P0171)
 7	enable IRQ14
 6	enable IRQ8
 5	enable IRQ7
 4	enable IRQ6
 3	enable IRQ5
 2	enable IRQ4
 1	enable IRQ3
 0	enable IRQ1
Note:	the value written into this register selects which IRQs generate
	  PMI#6 in normal mode, the value read from this register indicates
	  active IRQs at the time of the read
SeeAlso: #P0135,#P0159,#P0170

Bitfields for OPTi 82C463MV doze-mode configuration (register 65h):
Bit	Description	(Table P0172)
 7	enable monitoring all interrupt signals during hw or sw doze-mode
 6	doze-mode STPCLK protocol selector (see also #P0168)
	=1 STPCLK will latch for stopping the CPU clock (APM)
	     The delay is determined by register 61h bits 1-0
	=0 STPCLK will pulse for changing the frequency of the CPU clock
	  (hw doze-mode).
	     The pulse width is determined by register 61h bits 1-0
 5	enable EPMI1 to reload hardware DOZE_TIMER and exit from hardware or
	  software doze-mode
 4	enable recognition of SMI during APM stop clock
 3	allow IRQ1 to exit from hw or sw doze-mode (write-only)
	(see also #P0169)
 2-0	reserved (0)
SeeAlso: #P0135,#P0173

Bitfields for OPTi 82C463MV suspend control (register 66h):
Bit	Description	(Table P0173)
 7	refresh type during suspend
	=1 self refresh
	=0 normal refresh (refresh rate selected by register 67h bit 6)
 6	KBCLK during suspend
	=1 16 KHz
	=0 7.16 MHz (14.318 MHz /2)
 5	software (APM) CPU stop-clock control
	=1 the CPU clock can be stopped by entering APM doze-mode (that is
	  setting register 50h bit 3 to 1)
	=0 APM doze-mode will use the hw doze-mode clock selected by
	  bits 4-2 of register 41h
 4	avoid asserting HOLD before stopping the clock
 3	PIO3/STPGNT# pin selector
	=1 STPGNT# function (set register 57h bit 3 to input mode)
	    This is for use with CPUs that use the hw stop grant signal
	      to acknowledge stop request
	=0 PIO3 function (set register 57h bit 3 to determine input or
	  output mode)
 2	PIO2/CPUSPD pin selector
	=1 CPUSPD function, CPU speed indicator output (set register 57h
	  bit 2 to output mode)
	=0 PIO2 function (set register 57h bit 2 to determine input or
	  output mode)
 1	PIO1/NOWS# pin selector
	=1 NOWS# function (set register 57h bit 1 to input mode)
	=0 PIO1 function (set register 57h bit 1 to determine input or
	  output mode)
 0	enable CPU clock change request protocol
Note:	for hardware doze mode, bit 5 must be 0
SeeAlso: #P0135,#P0147,#P0154,#P0159,#P0174

Bitfields for OPTi 82C463MV CPU frequency (register 67h):
Bit(s)	Description	(Table P0174)
 7	CPU clock control during suspend
	=1 dynamic CPU (in suspend-mode, bits 2-0 select the CPU clock)
	=0 static CPU (in suspend-mode, 82C463MV stops the CPU clock)
 6	refresh control
	=1 slow refresh (128 ms)
	=0 normal refresh (15 ms for normal operation, 30 ms for suspend mode)
 5	PMU global enabler
 4	reserved (1)
 3	reserved (0)
 2-0	CPU clock frequency
	000 CPUCLK/1
	001 CPUCLK/2
	010 CPUCLK/4
	101 CPUCLK/3
	else reserved
SeeAlso: #P0135

Bitfields for OPTi 82C463MV timer clock source (register 68h):
Bit(s)	Description	(Table P0175)
 7-6	R_TIMER clock source selector
	00 SQW0
	01 SQW1
	10 SQW2
	11 SQW3
 5-4	IDLE_TIMER clock source selector (see bits 7-6)
 3-2	resume recovery time
	if register 40h bit 6 =1
	    00 8 ms
	    01 32 ms
	    10 128 ms
	    11 256 ms
	if register 40h bit 6 =0
	    00 2 ms
	    01 8 ms
	    10 32 ms
	    11 64 ms
 1	enable PPWR bit 1 suspend auto toggle (see also #P0156)
 0	enable PPWR bit 0 suspend auto toggle (see also #P0156)
Note:	bits 1 and 0 are not influenced by mask bits 5 and 4 of register 54h
SeeAlso: #P0135,#P0146

Bitfields for OPTi 82C463MV resume IRQ selects (register 6Ah):
Bit	Description	(Table P0176)
 7	enable EPMI2 (resume on a rising edge)
 6	enable EPMI1 (resume on a rising edge)
 5	enable IRQ8 (resume on a falling edge)
 4	enable IRQ7 (resume on a rising edge)
 3	enable IRQ5 (resume on a rising edge)
 2	enable IRQ4 (resume on a rising edge)
 1	enable IRQ3 (resume on a rising edge)
 0	enable IRQ1 (resume on a rising edge)
SeeAlso: #P0135

Bitfields for OPTi 82C463MV resume sources (register 6Bh):
Bit(s)	Description	(Table P0177)
 7	refresh pulse width during sequencer operation
	=1 6 AT clocks
	=0 4 AT clocks
 6-3	reserved (0)
 2-0	resume sources (read-only)
	001 RI
	010 INTR (as selected in register 6Ah)
	100 SUSP/RSM pin
	else reserved
SeeAlso: #P0135,#P0176

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P00220024 - PORT 0022-0024 - OPTi 82C493 System Controller (SYSC) - CONFIGURATION REGISTERS

PORT 0022-0024 - OPTi 82C493 System Controller (SYSC) - CONFIGURATION REGISTERS
Desc:	The OPTi 486SXWB contains three chips and is designed for systems
	  running at 20, 25 and 33MHz.	The chipset includes an 82C493 System
	  Controller (SYSC), the 82C392 Data Buffer Controller, and the
	  82C206 Integrated peripheral Controller (IPC).
Note:	every access to PORT 0024h must be preceded by a write to PORT 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  configuration register index (see #P0178)
0024  RW  configuration register data

(Table P0178)
Values for OPTi 82C493 System Controller configuration register index:
 20h	Control Register 1 (see #P0179)
 21h	Control Register 2 (see #P0180)
 22h	Shadow RAM Control Register 1 (see #P0181)
 23h	Shadow RAM Control Register 2 (see #P0182)
 24h	DRAM Control Register 1 (see #P0183)
 25h	DRAM Control Register 2 (see #P0184)
 26h	Shadow RAM Control Register 3 (see #P0185)
 27h	Control Register 3 (see #P0186)
 28h	Non-cachable Block 1 Register 1 (see #P0187)
 29h	Non-cachable Block 1 Register 2 (see #P0188)
 2Ah	Non-cachable Block 2 Register 1 (see #P0187)
 2Bh	Non-cachable Block 2 Register 2 (see #P0188)

Bitfields for OPTi-82C493 Control Register 1:
Bit(s)	Description	(Table P0179)
 7-6	Revision of 82C493 (readonly) (default=01)
 5	Burst wait state control
	1 = Secondary cache read hit cycle is 3-2-2-2 or 2-2-2-2
	0 = Secondary cache read hit cycle is 3-1-1-1 or 2-1-1-1 (default)
	(if bit 5 is set to 1, bit 4 must be set to 0)
 4	Cache memory data buffer output enable control
	0 = disable (default)
	1 = enable
	(must be disabled for frequency <= 33Mhz)
 3	Single Address Latch Enable (ALE)
	0 = disable (default)
	1 = enable
	(if enabled, SYSC will activate single ALE rather than multiples
	  during bus conversion cycles)
 2	enable Extra AT Cycle Wait State (default is 0 = disabled)
 1	Emulation keyboard Reset Control
	0 = disable (default)
	1 = enable
	Note:	This bit must be enabled in BIOS default value; enabling this
		  bit requires HALT instruction to be executed before SYSC
		  generates processor reset (CPURST)
 0	enable Alternative Fast Reset (default is 0 = disabled)
SeeAlso: #P0180,#P0186

Bitfields for OPTi-82C493 Control Register 2:
Bit(s)	Description	(Table P0180)
 7	Master Mode Byte Swap Enable
	0 = disable (default)
	1 = enable
 6	Emulation Keyboard Reset Delay Control
	0 = Generate reset pulse 2us later (default)
	1 = Generate reset pulse immediately
 5	disable Parity Check (default is 0 = enabled)
 4	Cache Enable
	0 = Cache disabled and DRAM burst mode enabled (default)
	1 = Cache enabled and DRAM burst mode disabled
 3-2	Cache Size
	00  64KB (default)
	01  128KB
	10  256KB
	11  512KB
 1	Secondary Cache Read Burst Cycles Control
	0 = 3-1-1-1 cycle (default)
	1 = 2-1-1-1 cycle
 0	Cache Write Wait State Control
	0 = 1 wait state (default)
	1 = 0 wait state
SeeAlso: #P0179,#P0186

Bitfields for OPTi-82C493 Shadow RAM Control Register 1:
Bit(s)	Description	(Table P0181)
 7	ROM(F0000h - FFFFFh) Enable
	0 = read/write on write-protected DRAM
	1 = read from ROM, write to DRAM (default)
 6	Shadow RAM at D0000h - EFFFFh Area
	0 = disable (default)
	1 = enable
 5	Shadow RAM at E0000h - EFFFFh Area
	0 = disable shadow RAM (default)
	    E0000h - EFFFFh ROM is defaulted to reside on XD bus
	1 = enable shadow RAM
 4	enable write-protect for Shadow RAM at D0000h - DFFFFh Area
	0 = disable (default)
	1 = enable
 3	enable write-protect for Shadow RAM at E0000h - EFFFFh Area
	0 = disable (default)
	1 = enable
 2	Hidden refresh enable (with holding CPU)
	(Hidden refresh must be disabled if 4Mx1 or 1M x4 bit DRAM are used)
	1 = disable (default)
	0 = enable
 1	unused
 0	enable Slow Refresh (four times slower than normal refresh)
	(default is 0 = disable)
SeeAlso: #P0182

Bitfields for OPTi-82C493 Shadow RAM Control Register 2:
Bit(s)	Description	(Table P0182)
 7	enable Shadow RAM at EC000h - EFFFFh area
 6	enable Shadow RAM at E8000h - EBFFFh area
 5	enable Shadow RAM at E4000h - E7FFFh area
 4	enable Shadow RAM at E0000h - E3FFFh area
 3	enable Shadow RAM at DC000h - DFFFFh area
 2	enable Shadow RAM at D8000h - DBFFFh area
 1	enable Shadow RAM at D4000h - D7FFFh area
 0	enable Shadow RAM at D0000h - D3FFFh area
Note:	the default is disabled (0) for all areas

Bitfields for OPTi-82C493 DRAM Control Register 1:
Bit(s)	Description	(Table P0183)
 7	DRAM size
	0 = 256K DRAM mode
	1 = 1M and 4M DRAM mode
 6-4	DRAM types used for bank0 and bank1
	bits 7-4  Bank0	  Bank1
	0000	  256K	     x
	0001	  256K	  256K
	0010	  256K	    1M
	0011	     x	     x
	01xx	     x	     x
	1000	    1M	     x	(default)
	1001	    1M	    1M
	1010	    1M	    4M
	1011	    4M	    1M
	1100	    4M	     x
	1101	    4M	    4M
	111x	     x	     x
 3	unused
 2-0	DRAM types used for bank2 and bank3
	bits 7,2-0  Bank2  Bank3
	x000	   1M	    x
	x001	   1M	   1M
	x010	    x	    x
	x011	   4M	   1M
	x100	   4M	    x
	x101	   4M	   4M
	x11x	    x	    x  (default)
SeeAlso: #P0184

Bitfields for OPTi-82C493 DRAM Control Register 2:
Bit(s)	Description	(Table P0184)
 7-6	Read cycle additional wait states
	00 not used
	01 = 0
	10 = 1
	11 = 2 (default)
 5-4	Write cycle additional wait states
	00 = 0
	01 = 1
	10 = 2
	11 = 3 (default)
 3	Fast decode enable
	0 = disable fast decode. DRAM base wait states not changed (default)
	1 = enable fast decode. DRAM base wait state is decreased by 1
	Note:	This function may be enabled in 20/25Mhz operation to speed up
		  DRAM access.	If bit 4 of index register 21h (cache enable
		  bit) is enabled, this bit is automatically disabled--even if
		  set to 1
 2	unused
 1-0	ATCLK selection
	00  ATCLK = CLKI/6 (default)
	01  ATCLK = CLKI/4 (default)
	10  ATCLK = CLKI/3
	11  ATCLK = CLK2I/5  (CLKI * 2 /5)
	Note:	bit 0 will reflect the BCLKS (pin 142) status and bit 1 will be
		  set to 0 when 82C493 is reset.
SeeAlso: #P0183,#P0185

Bitfields for OPTi-82C493 Shadow RAM Control Register 3:
Bit(s)	Description	(Table P0185)
 7	unused
 6	Shadow RAM copy enable for address C0000h - CFFFFh
	0 = Read/write at AT bus (default)
	1 = Read from AT bus and write into shadow RAM
 5	Shadow write protect at address C0000h - CFFFFh
	0 = Write protect disable (default)
	1 = Write protect enable
 4	enable Shadow RAM at C0000h - CFFFFh
 3	enable Shadow RAM at CC000h - CFFFFh
 2	enable Shadow RAM at C8000h - CBFFFh
 1	enable Shadow RAM at C4000h - C7FFFh
 0	enable Shadow RAM at C0000h - C3FFFh
Note:	the default is disabled (0) for bits 4-0
SeeAlso: #P0183,#P0184

Bitfields for OPTi-82C493 Control Register 3:
Bit(s)	Description	(Table P0186)
 7	enable NCA# pin to low state (default is 1 = enabled)
 6-5	unused
 4	Video BIOS at C0000h - C8000h non-cacheable
	0 = cacheable
	1 = non-cacheable (default)
 3-0	Cacheable address range for local memory
	0000  0 - 64MB
	0001  0 - 4MB (default)
	0010  0 - 8MB
	0011  0 - 12MB
	0100  0 - 16MB
	0101  0 - 20MB
	0110  0 - 24MB
	0111  0 - 28MB
	1000  0 - 32MB
	1001  0 - 36MB
	1010  0 - 40MB
	1011  0 - 44MB
	1100  0 - 48MB
	1101  0 - 52MB
	1110  0 - 56MB
	1111  0 - 60MB
	Note:	If total memory is 1MB or 2MB the cacheable range is 0-1 MB or
		  0-2 MB and independent of the value of bits 3-0
SeeAlso: #P0179,#P0180

Bitfields for OPTi-82C493 Non-cacheable Block Register 1:
Bit(s)	Description	(Table P0187)
 7-5	Size of non-cachable memory block
	000  64K
	001  128K
	010  256K
	011  512K
	1xx  disabled (default)
 4-2	unused
 1-0	Address bits 25 and 24 of non-cachable memory block (default = 00)
Note:	this register is used together with configuration register 29h
	  (non-cacheable block 1) or register 2Bh (block 2) (see #P0188) to
	  define a non-cacheable block.	 The starting address must be a
	  multiple of the block size
SeeAlso: #P0178,#P0188

Bitfields for OPTi-82C493 Non-cacheable Block Register 2:
Bit(s)	Description	(Table P0188)
 7-0	Address bits 23-16 of non-cachable memory block (default = 0001xxxx)
Note:	the block address is forced to be a multiple of the block size by
	  ignoring the appropriate number of the least-significant bits
SeeAlso: #P0178,#P0187

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P00220024 - PORT 0022-0024 - OPTi "Viper" (82C557) CHIPSET - SYSTEM CONTROL REGISTERS

PORT 0022-0024 - OPTi "Viper" (82C557) CHIPSET - SYSTEM CONTROL REGISTERS
Note:	every access to PORT 0024h must be preceded by a write to PORT 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  index for accesses to data port (see #P0189)
0023  RW  DMA clock select (see #P0087)
0024  RW  chip set data

(Table P0189)
Values for OPTi "Viper" (82C557) system control registers:
 00h	Byte Merge/Prefetch and Sony Cache Module Control register (see #P0190)
 00h	Compatible DRAM Configuration register 1 (see #P0191) (refer to note)
 01h	DRAM Control register 1 (see #P0192)
 02h	Cache Control register 1 (see #P0193)
 03h	Cache Control register 2 (see #P0194)
 04h	Shadow RAM Control register 1 (see #P0195)
 05h	Shadow RAM Control register 2 (see #P0197)
 06h	Shadow RAM Control register 3 (see #P0198)
 07h	Tag Test register (see #P0199)
 08h	CPU Cache Control register (see #P0200)
 09h	System Memory Function register (see #P0201)
 0Ah	DRAM Hole A Address Decode register 1 (see #P0202)
 0Bh	DRAM Hole B Address Decode register 2 (see #P0203)
 0Ch	Extended DMA register (see #P0204)
 0Dh	Clock Control register (see #P0205)
 0Eh	Cycle Control register 1 (see #P0206)
 0Fh	Cycle Control register 2 (see #P0207)
 10h	Miscellaneous Control register 1 (see #P0208)
 11h	Miscellaneous Control register 2 (see #P0209)
 12h	Refresh Control register (see #P0210)
 13h	Memory Decode Control register 1 (see #P0211)
 14h	Memory Decode Control register 2 (see #P0213)
 15h	PCI Cycle Control register 1 (see #P0214)
 16h	Dirty/Tag RAM Control register (see #P0215)
 17h	PCI Cycle Control register 2 (see #P0216)
 18h	Tristate Control register (see #P0217)
 19h	Memory Decode Control register 3 (see #P0218)
 1Ah-1Fh reserved
Note:	Byte Merge/Prefetch and Sony Cache Module Control register is accessed
	  through register 00h when bit 7 of register 13h is set, otherwise
	  Compatible DRAM Configuration register 1 is accessed as register 00h
	reserved registers 1Ah-1Fh must be written to 0
SeeAlso: #P0121,#P0211

Bitfields for OPTi "Viper" Byte Merge / Sony Cache Module Control register:
Bit(s)	Description	(Table P0190)
 7	enable pipelining of single CPU cycles to memory
 6	enable video memory byte/word read prefetch. Enables the prefetching
	  of bytes/words from PCI video memory to the CPU
 5	enable Sony SONIC-2WP support. If set, the ensure that the L2 cache
	  has been disabled (register 02h bits 3-2)
 4	enable byte/word merge support
 3	enable byte/word merging with CPU pipelining (NA# generation) support
 2-1	time-out counter for byte/word merge. Determines the maximum time
	  difference between two consecutive PCI bye/word writes to allow
	  merging
	00  4 CPU CLKs
	01  8 CPU CLKs
	10 12 CPU CLKs
	11 16 CPU CLKs
 0	enable internal hold requests to be blocked while performing byte merge
SeeAlso: #P0189

Bitfields for OPTi "Viper" Compatible DRAM Configuration register 1:
Bit(s)	Description	(Table P0191)
 7	enable pipelining of single CPU cycles to memory
 6	second bank SIMM selection. SIMMs need to be single sided
	0 single sided SIMM not installed in bank 0
	1 single sided SIMM installed in bank 0
 5	first bank SIMM selection. SIMMs need to be single sided
	0 single sided SIMM not installed in bank 0
	1 single sided SIMM installed in bank 0
 4-0	banks 0 thru 3 DRAM configuration
	(val)	Bank0	Bank1	Bank2	Bank3
	00000	256K	256KB	-	-
	00001	512K	512K	-	-
	00010	1M	1M	-	-
	00011	2M	2M	-	-
	00100	4M	4M	-	-
	00101	8M	8M	-	-
	00110	256K	256K	256K	256K
	00111	256K	256K	512K	512K
	01000	512K	512K	512K	512K
	01001	256K	256K	1M	1M
	01010	512K	512K	1M	1M
	01011	1M	1M	1M	1M
	01100	256K	256K	2M	2M
	01101	512K	512K	2M	2M
	01110	1M	1M	2M	2M
	01111	2M	2M	2M	2M
	10000	256K	256K	4M	4M
	10001	512K	512K	4M	4M
	10010	1M	1M	4M	4M
	10011	2M	2M	4M	4M
	10100	4M	4M	4M	4M
	10101	256K	256K	8M	8M
	10110	512K	512K	8M	8M
	10111	1M	1M	8M	8M
	11000	2M	2M	8M	8M
	11001	4M	4M	8M	8M
	11010	8M	8M	8M	8M
Note:	these settings maintain backward compatibility with the "Python"
	  (82C546/82C547) chipset, and they do not allow for much flexibility
SeeAlso: #P0189

Bitfields for OPTi "Viper" (82C557) DRAM Control register 1:
Bit(s)	Description	(Table P0192)
 7	row address hold after RAS# active in CLKs
	0 2 CLKs
	1 1 CLK
 6	RAS# active/inactive on entering master mode
	0 normal page mode when starting a master cycle, RAS# will remain
	1 RAS# inactive when starting a master cycle
 5-4	RAS pulse width used during refresh
	00 7 CLKs
	01 6 CLKs
	10 5 CLKs
	11 4 CLKs
 3	CAS pulse width during reads
	0 3 CLKs
	1 2 CLKs
 2	CAS pulse width during writes 
	0 3 CLKs
	1 2 CLKs
 1-0	RAS precharge time
	00 6 CLKs
	01 5 CLKs
	10 4 CLKs
	11 3 CLKs
SeeAlso: #P0189,#P0193,#P0219

Bitfields for OPTi "Viper" (82C557) Cache Control register 1:
Bit(s)	Description	(Table P0193)
 7-6	cache size selection; determines size of the L2 cache, along with
	  register 0Fh bit 0. When set, it works as a *16 multiplier
	00 (Viper)  64K (1M when register 0Fh bit 0 set)
	   (Vendetta) reserved
	01 (Viper) 128K (2M when register 0Fh bit 0 set)
	   (Vendetta) reserved
	10 256K (reserved when register 0Fh bit 0 set)
	11 512K (reserved when register 0Fh bit 0 set)
 5-4	cache write policy; determines the write policy for the L2 cache
	00 L2 cache write-through
	01 Adaptive Write-back Mode 1
	10 Adaptive Write-back Mode 2
	11 L2 cache write-back
 3-2	cache mode select; determines the operating mode of the L2 cache
	00 disable
	01 Test Mode 1, External Tag Write (Tag data write-through reg. 07h)
	10 Test Mode 2, External Tag Read (Tag data read from register 07h)
	11 enable L2 cache
 1	enable DRAM posted write
 0	CAS precharge time
	0 2 CLKs
	1 1 CLK
SeeAlso: #P0189,#P0199,#P0207,#P0194,#P0219

Bitfields for OPTi "Viper" (82C557) Cache Control register 2:
Bit(s)	Description	(Table P0194)
 7-6	L2 cache write burst mode timings
	00 X-4-4-4
	01 X-3-3-3
	10 X-2-2-2
	11 X-1-1-1
 5-4	L2 cache write lead-off cycle timings
	00 5-X-X-X
	01 4-X-X-X
	10 3-X-X-X
	11 2-X-X-X
 3-2	L2 cache read burst mode timings
	00 X-4-4-4
	01 X-3-3-3
	10 X-2-2-2
	11 X-1-1-1
 1-0	L2 cache read lead-off cycle timings
	00 5-X-X-X
	01 4-X-X-X
	10 3-X-X-X
	11 2-X-X-X
Note:	SRAM double bank implementation does not support lead-off timing
SeeAlso: #P0189,#P0193,#P0219

Bitfields for OPTi "Viper"/"Vendetta" Shadow RAM Control register 1:
Bit(s)	Description	(Table P0195)
 7-6	CC000-CFFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM (see #P0196)
 5-4	C8000-CBFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM (see #P0196)
 3	enable synchronous SRAM pipelined read cycle 1-1-1-1
 2	E0000-EFFFF range selection
	0 area will always be non-cacheable
	1 are will be treated like the F0000h BIOS area
 1-0	C0000-C7FFF read/write control; determines the R/W control for these
	  segments of the shadow RAM (see #P0196)
Note:	bit 3 will act only when register 11h bit 3 and register 03h bits 3-2
	  are all set
	when bit 2 is set, register 06h bits 3-0 should be set identically
SeeAlso: #P0189,#P0197,#P0219

(Table P0196)
Values for OPTi "Viper"/"Vendetta" Shadow RAM Control setting:
 00	read/write PCI bus
 01	read from DRAM/write to PCI
 10	read from PCI/write to DRAM
 11	read from/write to DRAM
SeeAlso: #P0195,#P0197,#P0198,#P0219

Bitfields for OPTi "Viper"/"Vendetta" Shadow RAM Control register 2:
Bit(s)	Description	(Table P0197)
 7-6	DC000-DFFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM (see #P0196)
 5-4	D8000-DBFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM (see #P0196)
 3-2	D4000-D7FFF read/write control; determines the R/W control for these
	  segments of the shadow RAM (see #P0196)
 1-0	D0000-D3FFF read/write control; determines the R/W control for these
	  segments of the shadow RAM (see #P0196)
SeeAlso: #P0189,#P0195,#P0198,#P0219

Bitfields for OPTi "Viper"/"Vendetta" Shadow RAM Control register 3:
Bit(s)	Description	(Table P0198)
 7	DRAM hole in system memory from 80000-9FFFF; gives the user the option
	  to have some other device in this address range instead of system
	  memory. When set, the SYSC will not start the system DRAM controller
	  for accesses to this particular address range
	0 no memory hole
	1 enable memory hole
 6	wait state addition for PCI master snooping
	0 do not add a wait state
	1 add a wait state for the cycle access to finish and then do snooping
 5	enable C0000-C7FFF cacheability in L1 and L2 cache memory
 4	enable F0000-FFFFF cacheability in L1 and L2 cache memory
 3-2	F0000-FFFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM (see #P0196)
 1-0	E0000-EFFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM (see #P0196)
Note:	L1 cacheability can be disabled thru register 08h bit 0
	If register 04h bit 2 is set, then F0000-FFFFF and E0000-EFFFF R/W
	control settings should have similar values
SeeAlso: #P0189,#P0197,#P0219

Bitfields for OPTi "Viper"/"Vendetta" Tag Test register:
Bit(s)	Description	(Table P0199)
 7-0	Tag Test register; when in cache Test Mode, data is read from/written
	  to this register
SeeAlso: #P0189,#P0193,#P0219

Bitfields for OPTi "Viper"/"Vendetta" CPU Cache Control register:
Bit(s)	Description	(Table P0200)
 7	L2 cache single/double bank select
	0 (Viper) two banks of L2 cache
	  (Vendetta) reserved
	1 single bank of L2 cache (non-interleaved)
 6	enable snoop filtering for bus masters
 5	CPU HITM# pin sample timing
	0 (Viper) delay one clock, therefore HITM# sampled on the third rising
	    edge of LCLK after EADS# has been asserted
	  (Vendetta) reserved
	1 do not delay, therefore HITM# sampled on the second rising edge
 4	enable parity checking
 3	Tag/Dirty RAM implementation
	0 (Viper) Tag and Dirty are on separate chips
	  (Vendetta) reserved
	1 Tag and Dirty are on the same chip
 2	enable CPU address pipelining
 1	enable L1 cache write-back and write-through control
	0 write-through only
	1 write-back enabled
 0	disable BIOS and Video BIOS areas cacheability in L1 cache
Notes:	If asynchronous SRAM, then cache memory banks (when two are present)
	  are interleaved, otherwise, they are not
	When register 04h bit 2 is set, bit 0 affects BIOS area
	  E0000-EFFFF; when clear, bit 0 affects area F0000-FFFFF
SeeAlso: #P0189,#P0201,#P0219

Bitfields for OPTi "Viper" (82C557) System Memory Function register:
Bit(s)	Description	(Table P0201)
 7-6	DRAM Hole B size
	(address specified by register 0Bh, and register 0Ch bits 3-2)
	00 512K
	01   1M
	10   2M
	11   4M
 5-4	DRAM Hole B control mode
	00 disable
	01 write-through for L1 and L2 cache
	10 non-cacheable for L1 and L2 cache
	11 enable hole in DRAM
 3-2	DRAM Hole A size (settings same as bits 7-6)
	(address specified by register 0Ah, and register 0Ch bits 1-0)
 1-0	DRAM Hole A control mode (settings same as bits 5-4)
SeeAlso: #P0189,#P0203,#P0204,#P0219

Bitfields for OPTi "Viper" (82C557) DRAM Hole A Address Decode register 1:
Bit(s)	Description	(Table P0202)
 7-0	DRAM Hole A address, bits 26-19
	(bits 1-0 of register 0Ch map onto bits 28-27 of HA lines)
SeeAlso: #P0189,#P0204,#P0203,#P0219

Bitfields for OPTi "Viper" (82C557) DRAM Hole B Address Decode register 2:
Bit(s)	Description	(Table P0203)
 7-0	DRAM Hole B address, bits 26-19
	(bits 3-2 of register 0Ch map onto bits 28-27 of HA lines)
SeeAlso: #P0189,#P0204,#P0202,#P0219

Bitfields for OPTi "Viper" (82C557) Extended DMA register:
Bit(s)	Description	(Table P0204)
 7	reserved (0)
 6	Fast BRDY# generation for DRAM write page hits
	0 BRDY# for DRAM writes generated on the fourth clock
	1 BRDY# for DRAM writes generated on the third clock
 5	(Viper) HACALE one-half a clock cycle earlier
	    0 HACALE normal timing
	    1 HACALE one-half a clock cycle early enabled
	(Vendetta) reserved
 4	(Viper) wider cache WE# pulse
	    0 cache WE# pulse width is normal (~15ns)
	    1 cache WE# pulse is wider (~17.5ns)
	(Vendetta) reserved
 3-2	DRAM Hole B starting address, bits 28-27 (see also #P0202)
 1-0	DRAM Hole A starting address, bits 28-27 (see also #P0203)
Note:	bits 26-19 of memory holes A and B are mapped from Indices 0Ah and 0Bh
SeeAlso: #P0189,#P0219

Bitfields for OPTi "Viper" (82C557) Clock Control register:
Bit(s)	Description	(Table P0205)
 7	(Viper) clock source for generation the syncronous SRAM timing
	    0 CPU clock is the source for the timing and control signals
	    1 ECLK is the source for the timing and control signals
	(Vendetta) reserved (1)
 6	(Viper) this bit is set if the skew between ECLK and CPU clock is too
	  large (read-only bit, set by the 82C557 chip)
	(Vendetta) reserved (read-only)
 5	(Viper) enable auto skew detect; when this bit is set, bit 4 will be
	  set automatically if the skew between CLK and ECLK is too large
	(Vendetta) BRDY# PCI-to-ISA bridge request remove BOFF# disable
 4	(Viper) ECLK - CLK skew, activated when synchronou SRAMs are being used
	    0 skew between CLK and ECLK is not too large
	    1 skew is too large
	(Vendetta) 
	    0 preemption when CPU needs memory
	    1 reserved
 3	enable A0000-BFFFF as system memory
 2	wait state addition for PCI master doing address toggling as a 486
	0 linear burst mode style address toggling - no wait state addition
	1 i486 burst style address toggling - one wait state needs to be added
 1	(Viper) PCI cycle claimed by the 82C557 during PCI pre-snoop cycle
	    0 82C557 does not claim the PCI cycle after it asserts STOP#
	    1 82C557 claims the PCI cycle after it asserts STOP#
	(Vendetta) reserved
 0	slow CPU clock; should be set if the CPU clock frequency has been
	  reduced
	    0 CPU clock frequency is normal
	    1 CPU clock has been slowed down
	(Vendetta) reserved
SeeAlso: #P0189,#P0219

Bitfields for OPTi "Viper" (82C557) Cycle Control register 1:
Bit(s)	Description	(Table P0206)
 7-6	(Viper) PCI master read burst wait state control
	    00 4 cycles
	    01 3 cycles
	    10 2 cycles
	    11 reserved
	(Vendetta) reserved
 5-4	(Viper) PCI master write burst wait state control (same settings as
	  bits 7-6)
	(Vendetta) reserved
 3	master cycle parity enable; this bit becomes applicable when bit 4 of
	  register 08h is set
	0 enable parity check during master cycles
	1 disable parity check during master cycles
 2	(Viper) HACALE timing control
	    0 HACALE high during HITM# before CPU ADS#
	    1 HACALE low and CA4 always enabled during HITM cycle
	(Vendetta) fast NA# generation enable
 1	enable write protection for L1 BIOS
 0	PCI line comparator; this bit is only valid when bit 6 of register 08h
	  is set
	0 use line comparator in PCI master
	1 generate inquire cycle for every new FRAME#
SeeAlso: #P0189,#P0219

Bitfields for OPTi "Viper" (82C557) Cycle Control register 2:
Bit(s)	Description	(Table P0207)
 7	enable PCI pre-snooping feature
 6	(Viper) AT master wait state control
	    0 do not add any wait states for AT master cycles
	    1 add wait wait states for AT master cycles
	(Vendetta) ISA master access wait states enable (use if PCICLK <33MHz)
 5	(Viper) wait state addition for synchronous SRAM even byte access
	    0 do not add a wait state for a synchronous SRAM even byte access
	    1 add one wait state for a synchronous SRAM even byte access
	(Vendetta) L2 write-through mode CPU-to-DRAM deep buffer enable
 4	PCI wait state addition for synchronous SRAM L2 cache implementation
	0 master does not wait for end of current cycle + CPU-PCI clock to
	  become synchronous
	1 master waits for end of current cycle + wait for CPU-PCI clock to
	  become synchronous
 3	(Viper) reserved
	(Vendetta) L2 single cycle write hit when line already dirty
	    0 = 5 CLKs
	    1 = 3 CLKs
 2	(Viper) ADSC# generation for synchronous SRAM read cycle
	    0 generate ADSC# immediately after CPU ADS# goes active
	    1 generate ADSC# one clock after CPU ADS# goes active
	(Vendetta) CPU to L2 cache hit cycle chipset ADSC# generation disable
 1	(Viper) reserved
	(Vendetta) two-PCI master fix
	    0 revision 2.0
 0	L2 cache size selector; works along with bits 1-0 of register 02h
	0 below 1M
	1 1M and above (Viper only)
SeeAlso: #P0189,#P0193,#P0219

Bitfields for OPTi "Viper" (82C557) Miscellaneous Control register 1:
Bit(s)	Description	(Table P0208)
 7	(Viper) early decode of PCI/VL/AT cycle
	(Vendetta) early decode of PCI/ISA cycle
	0 CPU to <bus> slave cycle triggered after second T2
	1 CPU to <bus> slave cycle triggered after first T2
 6	(Viper) cache modified write cycle timing
	    0 use the old address changing method, as in the 82C546/82C547
	    1 two bank cache, CA4 delayed one-half a clock for write cycles
	(Vendetta) reserved
 5	pipelined read cycle timing; determines the lead-off cycle
	0 3-X-X-X read followed by a 3-X-X-X piped read cycle
	1 3-X-X-X read followed by a 2-X-X-X piped read cycle
 4	(Viper) enable write hit pipelined
	    0 do not enable 2-X-X-X pipelined write hit cycles
	    1 enable 2-X-X-X pipelined write hit cycles
	(Vendetta) reserved
 3	(Viper) write pulse timing control for cache write hit cycles
	    0 do not change the write pulse timing during X-2-2-2 write hit
	      cycles
	    1 move the write pulse one-half a clock later in X-2-2-2 write hit
	      cycles
	(Vendetta) reserved
 2	(Viper) write pulse timing control for cache write hit cycles
	    0 do not change the write pulse timing during 3-X-X-X write hit
	      cycles
	    1 move the write pulse one-half a clock later in 3-X-X-X write hit
	      cycles
	(Vendetta) reserved
 1	(Viper) external 74F126 select
	    0 an external 74F126 is installed for CA3 and CA4
	    1 an external 74F126 is not installed for CA3 and CA4
	(Vendetta) reserved (1)
 0	LCLK select control; when this bit is set, the timing constraints
	  between the LCLK and the CPUCLK inputs to the SYSC need to be met.
	  This constraints are: LCLK <= 1/2 CPUCLK period before CPUCLK, and
	  LCLK <= 0.5ns after CPUCLK
	0 LCLK is asynchronous to the CPUCLK
	1 LCLK is synchronous to the CPUCLK; LCLK = CPUCLK/2
Note:	bit 1 should always be set to 1
SeeAlso: #P0189,#P0219

Bitfields for OPTi "Viper" (82C557) Miscellaneous Control register 2:
Bit(s)	Description	(Table P0209)
 7-6	reserved; must be set to 0
 5	cache inactive during Idle state control
	0 SRAM always active
	1 SRAM inactive during Idle state (Viper only)
 4	next address (NA#) mode control
	0 normal NA# timing used with asynchronous SRAMs
	1 new NA# timing for synchronous SRAMs; used only when CPU operating
	  at 50MHz
 3	SRAM type
	0 asynchronous SRAM (Viper only)
	1 synchronous SRAM
 2	(Viper) enable page miss posted write
	(Vendetta) reserved
 1	(Viper) ISA/DMA IOCHRDY control
	    0 old mode, no IOCHRDY during line hit
	    1 drive IOCHRDY low until cycle is finished
	(Vendetta) reserved
 0	(Viper) delay start
	    0 old mode, do not delay internal master cycle after an inquire
	      cycle
	    1 delay internal master cycles by one LCLK after an inquire cycle
	(Vendetta) reserved
SeeAlso: #P0189,#P0219

Bitfields for OPTi "Viper" (82C557) Refresh Control register:
Bit(s)	Description	(Table P0210)
 7	REFRESH#/32KHz source selection
	0 REFRESH# source is REFRESH# pulse from the 82C558 or the ISA master
	1 REFRESH# pulse source is a 32KHz clock
 6	reserved; must be written to 0
 5-4	suspend mode refresh
	00 from CLK state machine
	01 slef refresh based on 32KHz only
	10 normal refresh based on 32KHz only
	11 undefined
 3-2	slow refresh
	00 refresh on every REFRESH#/32KHz falling edge
	01 refresh on alternate REFRESH#/32KHz falling edge
	10 refresh on one in four REFRESH#/32KHz falling edge
	1 refresh on every REFRESH#/32KHz toggle
 1	enable bits 23-17 of LA from Refresh Page register (8Fh) during refresh
 0	enable output of bits 7-4 of DBC MP during master write
	0 disable the DBC from generation the MP[7:4] lines during PCI master
	  writes; there must be a pull-up on MP0
	1 enable the DBC to generate the MP[7:4] lines during PIC master
	  writes; there must be a pull-down on MP0
SeeAlso: #P0189,#P0211

Bitfields for OPTi "Viper" (82C557) Memory Decode Control register 1:
Bit(s)	Description	(Table P0211)
 7	(Viper) memory decode select
	0 Byte Merge/Prefetch and Sony Cache Module Control register is
	  available in register 00h; compatible to 82C547 DRAM configurations
	1 Compatible DRAM Configuration register is available in register 00h;
	  full decode option; this gives the user maximum flexibility in
	  choosing different DRAM configurations
	(Vendetta) reserved (1)
 6-4	full decode for logical bank 1 (RAS#1), if bit 7 set. This settings
	  apply to 36-pin banks only (see #P0212)
 3	enable SMRAM
 2-0	full decode for logical bank 0 (RAS#0), if bit 7 set. This settings
	  apply to 36-pin banks only (see #P0212)
SeeAlso: #P0189,#P0190,#P0191,#P0219

(Table P0212)
Values for OPTi "Viper" (82C557) Memory Bank Decode Control registers:
 000	  0K
 001	256K
 010	512K
 011	  1M
 100	  2M
 101	  4M
 110	  8M
 111	 16M
SeeAlso: #P0211,#P0213,#P0216

Bitfields for OPTi "Viper" (82C557) Memory Decode Control register 2:
Bit(s)	Description	(Table P0213)
 7	(Viper) reserved; must be written to 0
	(Vendetta) reserved (1)
 6-4	full decode for logical bank 3 (RAS#3), if register 13h bit 7 is set
	  (see #P0212)
 3	SMRAM control
	0 disable SMRAM (enable SMRAM for both Code and Data if SMIACT# is
	  active and register 13h bit 3 is set)
	1 enable SMRAM (enable SMRAM for Code only if SMIACT# is active and
	  register 13h bit 3 is set)
 2-0	full decode for logical bank 2 (RAS#2), if register 13h bit 7 is set
	  (see #P0212)
SeeAlso: #P0189,#P0219

Bitfields for OPTi "Viper" (82C557) PCI Cycle Control register 1:
Bit(s)	Description	(Table P0214)
 7-6	CPU master to PCI memory slave, write IRDY# control
	00 3 LCLKs after end of address phase
	01 2 LCLKs after end of address phase
	10 1 LCLK after end of address phase
	11 0 LCLK after end of address phase
 5-4	CPU master to PCI slave write posting, bursting control
	00 PCI slave write, no posting, no bursting
	01 PCI slave write, posting enabled, no bursting
	10 PCI slave write, posting enabled, conservative bursting
	11 PCI slave write, posting enabled, aggressive bursting
 3-2	master retry timer
	00 retries unmasked after 10 PCICLKs
	01 retries unmasked after 18 PCICLKs
	10 retries unmasked after 34 PCICLKs
	11 retries unmasked after 66 PCICLKs
 1	reserved; must be written to 0
 0	PCI cycle, FRAME# timing control for pipelined cycles
	0 PCI cycle FRAME# assertion is done in the conservative mode style
	1 PCI cycle FRAME# assertion is done in the aggressive mode style
SeeAlso: #P0189,#P0216,#P0219

Bitfields for OPTi "Viper"/"Vendetta" Dirty/Tag RAM Control register:
Bit(s)	Description	(Table P0215)
 7	(Viper) Dirty pin selection; reflects the kind of SRAM chosen to
	  implement the Dirty RAM; it also determines the functionality of the
	  DIRTYI pin of the 82C557
	    0 DIRTYI pin is input-only
	    1 DIRTYI pin is bidirectional
	(Vendetta) reserved (1)
 6	reserved; must be written to 0
 5	Tag RAM size
	0 = 8-bit Tag (Viper only)
	1 = 7-bit Tag
 4	write hit cycle lead-off time when combining Dirty/Tag RAM
	0 single write hit lead-off cycle = 5 cycles
	1 single write hit lead-off cycle = 4 cycles
 3	pre-snoop control
	0 pre-snoop for starting address 0 only
	1 pre-snoop for all addresses except those on the line boundary
 2	(Viper) reserved; must be written to 0
	(Vendetta) synchronization between LCLK and CLK
	    0 LCLK is asynchronous to CLK
	    1 LCLK is synchronous to CLK
 1	(Viper) CPU to VL read access, DBC DLE# bits 1-0 timing
	    0 LCLK high
	    1 LCLK low
	(Vendetta) reserved
 0	(Viper) HDOE# timing control
	    0 HDOE# is negated normally
	    1 HDOE# is negated one clock before the cycle finishes
	(Vendetta) reserved
Note:	(Vendetta) bit 4 should be set same as register 22h bit 0
SeeAlso: #P0189,#P0219

Bitfields for OPTi "Viper"/"Vendetta" PCI Cycle Control register 2:
Bit(s)	Description	(Table P0216)
 7	(Vipder) NA# assertion control for PCI slave accesses when synchronous
	  PCI clock is used
	    0 no pipelining for accesses to PCI slave
	    1 pipelining enabled for accesses to PCI slave for both synchronous
	      and asynchronous PCI solutions; if set, overrides bit 6
	(Vendetta) MD drive strength
	    0 =	 8 mA
	    1 = 12 mA
 6	NA# assertion control for PCI slave accesses when asynchronous PCI
	  clock is used
	0 no pipelining for accesses to PCI slave
	1 pipelining enabled for accesses to PCI slave for an asynchronous PCI
	  implementation; this bit is overridden if bit 7 is set
 5	(Viper) enable support for Intel standard BSRAM
	    0 no support for Intel standard BSRAM
	    1 support for Intel standard BSRAM; should be set only if using two
	      banks of synchronous SRAM
	(Vendetta) reserved
 4	(Viper only) enable fast BRDY# generation for PCI cycles
 3	(Viper only) enable fast FRAME# generation for PCI cycles	    
 2	(Viper only) byte merging/piping control
	0 no pipelining when byte merging is on
	1 pipelining enabled along with byte merging
 1	pipelined synchronous SRAM support; this bit is applicable only if
	  register 11h bit 3 is set
	0 standard synchronous SRAM installed (Viper only)
	1 pipelined synchronous SRAM installed
 0	Cyrix linear burst mode support
	0 normal Intel standard burst mode
	1 support for Cyrix linear burst mode
SeeAlso: #P0189,#P0214,#P0219

Bitfields for OPTi "Viper"/"Vendetta" Tristate Control register:
Bit(s)	Description	(Table P0217)
  7	(Viper) reserved; must be written to 0
	(Vendetta) ISA retry (1)
 6	(Viper) reserved; must be written to 0
	(Vendetta) RAS line drive strength
	    0 = 16 mA
	    1 =	 4 mA
 5	(Viper) voltage selection for the CAS# lines 7-0
	    0 CAS# lines 7-0 are driven out at 5.0V logic level
	    1 CAS# lines 7-0 are driven out at 3.3V logic level
	(Vendetta) CAS1# and CAS5# drive strength
	    0 =	 8 mA
	    1 = 16 mA
 4	(Viper) programmable current drive for the MA[X], RAS[X]# and the DWE#
	  lines
	(Vendetta) memory address lines and write enable line drive strength
	0 driving capability on these lines is 4mA
	1 driving capability on these lines is 16mA
 3	enable tristate CPU interface during Suspend and during CPU power-off
 2	enable tristate PCI interface during Suspend and during PCI power-off
 1	enable tristate cache interface during Suspend and cache power-off
 0	enable the pull-up/pull-down resistors during Suspend and power-off
SeeAlso: #P0189,#P0219

Bitfields for OPTi "Viper" (82C557) Memory Decode Control register 3:
Bit(s)	Description	(Table P0218)
 7	DIRTYWE# RAS5# selection; if six DRAM banks are chosen, then the line
	  will become RAS#5, if this bit is set
	0 DIRTYWE# functions as DIRTYWE# (six banks of DRAM are not chosen)
	1 DIRTYWE# functions as RAS#5 (six banks of DRAM are chosen)
	(Vendetta must be set to RAS5# function (1))
 6-4	(Viper) full decode for logical bank 5 (RAS#5) if register 13h bit 7
	  and register 19h bit 7 are set (see #P0212)
	(Vendetta) full decode for logical bank 5 (RAS5#) if register 13h
	  bit 7 set (see #P0212)
 3	MA11/RAS#4 selection; if five DRAM banks are chosen, then the MA11 line
	  will become RAS#4, if this bit is set
	0 MA11 functions as MA11 (the fifth bank of DRAM is not chosen)
	1 MA11 functions as RAS#4 (five banks of DRAM have been chosen)
	(Vendetta must be set to RAS4# function (1))
 2-0	(Viper) full decode for logical bank 4 (RAS#4) if register 13h bit 7
	  and register 19h bit 3 are set (see #P0212)
	(Vendetta) full decode for logical bank 4 (RAS4#) if register 13h
	  bit 7 set (see #P0212)
Notes:	(Viper) if bit 7 is set, then a combined Dirty/Tag SRAM solution must
	   be implemented or else it will not have a Dirty RAM
	(Viper) if bit 3 is set, then none of the DRAM banks will support the
	  8M*36 or 16M*36 options
SeeAlso: #P0189,#P0219

Top

P00220024 - PORT 0022-0024 - OPTi "Vendetta" (82C750) CHIPSET - SYSTEM CONTROL REGISTERS

PORT 0022-0024 - OPTi "Vendetta" (82C750) CHIPSET - SYSTEM CONTROL REGISTERS
Note:	every access to PORT 0024h must be preceded by a write to PORT 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORT 0022h"82C206"

0022  ?W  index for accesses to data port (see #P0219)
0023  RW  DMA clock select (see #P0087)
0024  RW  chip set data

(Table P0219)
Values for OPTi "Vendetta" (82C750) system control registers:
 00h	DRAM control register 1 (see #P0220)
 01h	DRAM control register 2 (see #P0192)
 02h	cache control register 1 (see #P0193)
 03h	cache control 2 (see #P0194)
 04h	shadow RAM control register 1 (see #P0195)
 05h	shadow RAM control register 2 (see #P0197)
 06h	shadow RAM control register 3 (see #P0198)
 07h	tag test register (see #P0199)
 08h	CPU cache control register (see #P0200)
 09h	system memory function register (see #P0201)
 0Ah	DRAM hole A address decode register 1 (see #P0202)
 0Bh	DRAM hole B address decode register 2 (see #P0203)
 0Ch	DRAM hole higher address (see #P0204)
 0Dh	clock control register (see #P0205)
 0Eh	PCI master burst control register 1 (see #P0206)
 0Fh	PCI master burst control register 2 (see #P0207)
 10h	miscellaneous control register 1 (see #P0208)
 11h	miscellaneous control register 2 (see #P0209)
 12h	miscellaneous control register 3 (see #P0221)
 13h	memory decode control register 1 (see #P0211)
 14h	memory decode control register 2 (see #P0213)
 15h	PCI cycle control register 1 (see #P0214)
 16h	dirty/tag RAM control register (see #P0215)
 17h	PCI cycle control register 2 (see #P0216)
 18h	tristate control register (see #P0217)
 19h	memory decode control register 3 (see #P0218)
 1Ah	memory shadow control register 1 (see #P0222)
 1Bh	memory shadow control register 2 (see #P0223)
 1Ch	EDO SDRAM control register (see #P0224)
 1Dh	miscellaneous control register 4 (see #P0225)
 1Eh	BOFF# control register (see #P0226)
 1Fh	EDO timing control register (see #P0227)
 20h	DRAM burst control register (see #P0228)
 21h	PCI concurrence control register (see #P0229)
 22h	inquire cycle control register (see #P0230)
 23h	pre-snoop control register (see #P0231)
 24h	asymmetric DRAM configuration register (see #P0232)
 25h	GUI memory location register (see #P0233)
 26h	UMA control register (see #P0234)
 27h	self refresh timing register (see #P0235)
 28h	SDRAM burst and latency control register (see #P0236)
 29h	SDRAM selection register (see #P0237)
 2Ah	PCI-to-DRAM deep buffer size register (see #P0238)
 2Bh	EDO/SDRAM time-out register (see #P0239)
 2Ch	CPU-to-DRAM buffer control register (see #P0240)
 2Dh	bank-wise EDO timing selection register (see #P0241)
 2Eh	PCI master - GUI retry control register (see #P0242)
 2Fh	CAS address setup time control register (see #P0243)
 30h-7Fh reserved
 80h	PIC 1 ICW1 read-back register (read-only)
 81h	PIC 1 ICW2 read-back register (read-only)
 82h	PIC 1 ICW3 read-back register (read-only)
 83h	PIC 1 ICW4 read-back register (read-only)
 84h	reserved
 85h	PIC 1 OCW2 read-back register (read-only)
 86h	PIC 1 OCW3 read-back register (read-only)
 87h	reserved
 88h	PIC 2 ICW1 read-back register (read-only)
 89h	PIC 2 ICW2 read-back register (read-only)
 8Ah	PIC 2 ICW3 read-back register (read-only)
 8Bh	PIC 2 ICW4 read-back register (read-only)
 8Ch	reserved
 8Dh	PIC 2 OCW2 read-back register (read-only)
 8Eh	PIC 2 OCW3 read-back register (read-only)
 8Fh	refresh address register (see #P0244)
 90h	CTSC0LB (PIT counter 0 low byte) read-back register (read-only)
 91h	CTSC0HB (PIT counter 0 high byte) read-back register (read-only)
 92h	CTSC1LB (PIT counter 1 low byte) read-back register (read-only)
 93h	CTSC1HB (PIT counter 1 high byte) read-back register (read-only)
 94h	CTSC2LB (PIT counter 2 low byte) read-back register (read-only)
 95h	CTSC2HB (PIT counter 2 high byte) read-back register (read-only)
 96h	byte pointer register (read-only)
	(byte 2 pointer value)
 97h-ACh reserved
 ADh	general purpose chip select control register (see #P0270)
 AEh-DFh reserved
 E0h	GREEN mode control/enable status (see #P0245)
 E1h	EPMI control/GREEN event timer (see #P0246)
 E2h	GREEN event timer initial count register (see #P0247)
 E3h	IRQ event enable register 1 (see #P0248)
 E4h	IRQ event enable register 2 (see #P0249)
 E5h	DREQ event enable register (see #P0250)
 E6h	device cycle monitor enable register (see #P0251)
 E7h	wake-up source/programmable IO/memory address mask register (see #P0252)
 E8h	programmable I/O/MEM address range register (see #P0253)
 E9h	programmable I/O/MEM address range register (see #P0254)
 EAh	enter GREEN state port register (see #P0255)
 EBh	return to NORMAL state configuration port register (see #P0256)
 ECh	shadow register for external power control latch register (see #P0257)
 EDh	device cycle detection enable/status register (see #P0258)
 EEh	STPCLK# modulation register (see #P0259)
 EFh	miscellaneous register (see #P0260)
 F0h	device timer CLK select/enable status register (see #P0261)
 F1h	device timer 0 initial count register
 F2h	device timer 1 initial count register
 F3h	device timer IO/MEM select, mask bits register (see #P0262)
 F4h	device 0 IO/MEM address register (see #P0263)
 F5h	device 0 IO/MEM address register (see #P0264)
 F6h	device 1 IO/MEM address register (see #P0265)
 F7h	device 1 IO/MEM address register (see #P0266)
 FAh-FBh reserved
 FCh	power management control register 1 (see #P0267)
 FDh	power management control register 2 (see #P0268)
 FEh	power management control register 3 (see #P0269)
 FFh	general purpose chip select control register (see #P0270)

Bitfields for OPTi "Vendetta" DRAM control register 1:
Bit(s)	Description	(Table P0220)
 7	reserved
 6	SDRAM pipeline fix (1)
 5-0	reserved
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" miscellaneous control register 3:
Bit(s)	Description	(Table P0221)
 7	buffered DMA register 8Fh latch to bits 23-16 of SA lines disable
 6-0	reserved
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" memory shadow control register 1:
Bit(s)	Description	(Table P0222)
 7	reserved
 6-5	CPU bus utilization time guarantee
	00 = no guarantee
	01 = 1 of every 15 microseconds
	10 = 2 of every 15 microseconds
	11 = 4 of every 15 microseconds
 4	C8000-DFFFF shadow granularity
	0 = 16 KB
	1 =  8 KB
 3-2	CE000-CFFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM; applicable if bit 4 is set (see #P0196)
 1-0	CA000-CBFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM; applicable if bit 4 is set (see #P0196)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" memory shadow control register 2:
Bit(s)	Description	(Table P0223)
 7-6	DE000-DFFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM; applicable if register 1Ah bit 4 is set
	  (see #P0196)
 5-4	DA000-DBFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM; applicable if register 1Ah bit 4 is set
	  (see #P0196)
 3-2	D6000-D7FFF read/write control; determines the R/W control for these
	  segments of the shadow RAM; applicable if register 1Ah bit 4 is set
	  (see #P0196)
 1-0	D2000-D3FFF read/write control; determines the R/W control for these
	  segments of the shadow RAM; applicable if register 1Ah bit 4 is set
	  (see #P0196)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" EDO SDRAM control register:
Bit(s)	Description	(Table P0224)
 7-2	bank 5-0 EDO SDRAM usage
	0 = standard page mode DRAM
	1 = EDO SDRAM
 1	reserved
 0	DRAM access CAS pulse width
	0 = determined by register 01h bit 3
	1 = 1 CPUCLK
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" miscellaneous control register 4:
Bit(s)	Description	(Table P0225)
 7-6	reserved
 5	DWE# timing
	0 = normal
	1 = removed 1 CLK earlier
 4	DRAM read leadoff cycle
	0 = normal
	1 = 1 CLK reduced
 3	system memory DMA access disable
 2	reserved
 1	SMM mode B0000-BFFFF access
	0 = main memory
	1 = PCI bus
 0	SMM mode A0000-AFFFF access
	0 = main memory
	1 = PCI bus
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" BOFF# control register:
Bit(s)	Description	(Table P0226)
 7	PCI master read cycle
	0 = wait IRDY# assert before TRDY# assert
	1 = generate TRDY# when checking IRDY# status
 6	reserved (1)
 5	reserved
 4	A0000-BFFFF PCI retry cycle BOFF# generation
	0 = not generated if bit 3 set
	1 = generated if bit 3 set
 3	deadlock situation avert
	0 = no avert
	1 = assert BOFF#
 2	reserved (1)
 1-0	reserved
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" EDO timing control register:
Bit(s)	Description	(Table P0227)
 7	0 = normal
	1 = EDO detection conflict generation (bit 6 set)
 6	0 = normal fast page mode
	1 = detect EDO
 5	NA# generation
	0 = aggresive
	1 = normal
 4	DRAM read cycle lead-off 1 CLK reduce enable
 3-2	reserved
 1	hidden refresh block AHOLD disable
 0	D0000-DFFFF cacheable in L1 and L2
	0 = not cacheable
	1 = cacheable; area has to be read/writable and shadowed
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" DRAM burst control register:
Bit(s)	Description	(Table P0228)
 7	reserved (1)
 6	PCI master access HITM# cycle DRAM write post enable
 5	reserved
 4	PCI master parity enable
 3-2	PCI master cycle DRAM write burst cycle
	00 = reserved
	01 = X-3-3-3
	10 = X-2-2-2
	11 = X-1-1-1
 1-0	PCI master cycle DRAM read burst cycle
	00 = reserved
	01 = X-3-3-3
	10 = X-2-2-2
	11 = X-1-1-1
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" PCI concurrence control register:
Bit(s)	Description	(Table P0229)
 7	concurrence timer
	0 = conservative
	1 = aggressive
 6-5	PCI master and CPU/L2 concurrence
	00 = no concurrence
	x1 = PCI write invalid cycles
	1x = PCI read multiple and read line cycles
 4-3	reserved
 2	0 = if tag = 11011111b => invalid combination
	1 = if cache = 256K, tag = 00001100b => invalid combination (CF0000h).
	    if cache > 256K, tag = 10111111b => invalid combination
	  (valid only when bit 1 set)
 1-0	reserved (1)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" inquire cycle control register:
Bit(s)	Description	(Table P0230)
 7	reserved
 6-5	new mode pre-snoop function
	00 = disable
	11 = enable
 4	HRQ synchronous to LCLK enable (must be 1 for ISA retry)
 3-1	reserved
 0	write hit cycle lead-off time when combining Dirty/Tag RAM
	0 = single write hit lead-off cycle = 5 cycles
	1 = single write hit lead-off cycle = 4 cycles
Note:	bit 0 should be set same as register 16h bit 4
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" pre-snoop control register:
Bit(s)	Description	(Table P0231)
 7	reserved
 6	0 = bank 0 selected as first bank
	1 = bank 0 selected as last bank
 5	PCI X-1-1-1 write invalidate pre-snoop enable
 4	PCI X-1-1-1 read multiple and read line pre-snoop enable
 3	fast NA cache hit half clock shift enable
 2-1	reserved (1)
 0	reserved
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" asymmetric DRAM configuration register:
Bit(s)	Description	(Table P0232)
 7-6	logical bank 3 DRAM type
	00 = symmetric
	01 = asymmetric x8
	10 = asymmetric x9
	11 = asymmetric x10
 5-4	logical bank 2 DRAM type
 3-2	logical bank 1 DRAM type
 1-0	logical bank 0 DRAM type
Note:	banks 4 and 5 do not support asymmetric DRAM
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" GUI memory location register:
Bit(s)	Description	(Table P0233)
 7-3	GUI memory location bits 31-27
 2	UMA size
	0 = decided by register 26h bits 5-4
	1 = 0.5MB (register 26h bits 5-4 = 00)
 1-0	reserved
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" UMA control register:
Bit(s)	Description	(Table P0234)
 7	ISA master to DRAM cycle CAS width
	0 = controlled by ISA read/write command pulse width
	1 = 2 LCLKs
 6	ISA SA address latch
	0 = pass-through
	1 = on only for retry
 5-4	GUI memory size
	00 = 1MB (0.5MB if register 25h bit 2 set)
	01 = 2MB
	10 = 3MB
	11 = 4MB
 3	66MHz 5-2-2-2 EDO DRAM read timing enable
 2-1	GUI priority
	00 = normal
	01 = wait 2 CLKs for low priority GUI request
	11 = high
 0	UMA support enable
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" self refresh timing register:
Bit(s)	Description	(Table P0235)
 7-6	reserved
 5	PCI master write line invalid cycle HITM# or L2 dirty no stop enable
 4	CPU single write hit not dirty cycle second T2 AHOLD generate enable
 3	fast NA# with L2 cache enable
 2-0	self refresh
	000 = disable, use external refresh pin
	001-011 = reserved
	100 = 66MHz external CPU clock
	101 = 60MHz external CPU clock
	110 = 50MHz external CPU clock
	111 = 40MHz external CPU clock
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" SDRAM burst and latency control register:
Bit(s)	Description	(Table P0236)
 7	CS# delay enable
 6-4	SDRAM CAS# latency
	000 = reserved
	001 = 1
	010 = 2
	011 = 3
	100-111 = reserved
 3	0 = sequential write-through
	1 = interleaved write-through
 2-0	SDRAM burst length
	000 = 1
	001 = reserved
	010 = 4
	011-111 = reserved
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" SDRAM selection register:
Bit(s)	Description	(Table P0237)
 7	pipeline read
	0 = 7-1-1-1-5-1-1-1-1
	1 = 7-1-1-1-2-1-1-1-1
 6	reserved
 5	timing
	     tRP     tRAS    tMRS
	00 = 2 CLKs  4 CLKs  3 CLKs
	01 = 4 CLKs  5 CLKs  3 CLKs
	10 = 3 CLKs  6 CLKs  2 CLKs
	11 = rsvd    7 CLKs  rsvd
	tRP: command activate precharge time
	tRAS: command precharge RAS active time
	tMRS: mode register set cycle time
 4-0	bank 4-0 SDRAM enable
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" PCI-to-DRAM deep buffer size register:
Bit(s)	Description	(Table P0238)
 7	reserved
 6-5	PCI master read cycle GUI request time-out
	00 = FP mode, grant DRAM bus when possible
	01 = SDRAM or EDO time-out
	10-11 = FP mode, SDRAM, or EDO time-out
 4	PCI-to-DRAM deep buffer PCI TRDY# wait state
	0 = 0 wait state (X-1-1-1)
	1 = 1 wait state (X-2-2-2)
 3	PCI-to-DRAM deep buffer write burst enable
 2	PCI-to-DRAM deep buffer read burst enable
 1-0	PCI-to-DRAM deep buffer size
	00 = 16 dwords
	01 = 24 dwords
	10-11 = reserved
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" EDO/SDRAM time-out register:
Bit(s)	Description	(Table P0239)
 7-4	SDRAM time-out count on GUI request - 9 CLKs
	  (delay count +9 CLKs)
 3-0	EDO time-out count on GUI request
	  (delay count +6 CLKs)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" CPU-to-DRAM buffer control register:
Bit(s)	Description	(Table P0240)
 7	concurrent CPU-to-PCI read and CPU-to-DRAM write enable
 6	reserved
 5	cache miss dirty cycle CPU-to-DRAM buffer control
	1 = supply data to CPU before previous data write-back
	  (CPU-to-DRAM buffer must be enabled)
 4-3	reserved
 2	DRAM read cycle BOFF# assert enable
 1	CPU DRAM bus ownership data merge enable
 0	write data while buffer flush enable
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" bank-wise EDO timing selection register:
Bit(s)	Description	(Table P0241)
 7	reserved
 6	predictive reading enable
 5-0	bank 5-0 EDO DRAM read cycle
	0 = default
	1 = 5-X-X-X (66MHz)/4-X-X-X (50MHz) enable
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" PCI master - GUI retry control register:
Bit(s)	Description	(Table P0242)
 7-6	reserved
 5	USB module enable
 4	reserved
 3	CPU-to-PCI FIFO control module enable
 2	reserved
 1	PCI master HITM# cycle, GUI high priority request before first BRDY#
	0 = retry all
	1 = retry only PCI master read
 0	GUI cycle PCI master request retry
	0 = retry all
	1 = retry reads, accept writes
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" CAS address setup time control register:
Bit(s)	Description	(Table P0243)
 7	page miss cycle CAS column address delay
	0 = default
	1 = 1 CLK
 6	burst mode and length
 5	reserved
 4-3	burst mode and length
	bits 6 and 4-3:
	000 = mode 0, RWM 5
	001 = mode 1, RWM 5, BLEN 2
	010 = BLEN 3
	011 = BLEN 4
	100 = mode 0, RWM 4
	101 = mode 2, RWM 4, BLEN 1
	110 = BLEN 2
	111 = BLEN 3
	RWM: refresh request water mark
	BLEN: minimum number of burst refresh cycles
	mode 0: generate refresh request on RWM reach/cross; if high priority
		GUI request pending, preempt refresh burst at end of current
		cycle; if CPU/PCI request pending, preempt refresh burst when
		count<RWM; else refresh until count=0, then refresh ahead up
		to 3/7
	mode 1: generate refresh request on RWM reach/cross; if high priority
		GUI request pending, preempt refresh burst at end of current
		cycle; if CPU/PCI request pending, preempt refresh burst when
		count<RWM and performed refresh cycles>=BLEN; else refresh
		until count=0, then refresh ahead up to 3/7
	mode 2: generate refresh request on RWM reach/cross; if high priority
		GUI request pending, preempt refresh burst at end of current
		cycle; if CPU request pending, preempt refresh burst when
		performed refresh cycles>=BLEN; if PCI request pending,
		preempt refresh burst when count<RWM and performed refresh
		cycles>=BLEN; else refresh until count=0, then refresh ahead
		up to 3/7
 2-0	refresh ahead
	000 = burst refresh disable
	001 = starting bank 0, no refresh ahead
	010 = starting bank 0, refresh ahead up to 3
	011 = starting bank 0, refresh ahead up to 7
	100 = burst refresh disable
	101 = starting bank dynamic, no refresh ahead
	110 = starting bank dynamic, refresh ahead up to 3
	111 = starting bank dynamic, refresh ahead up to 7
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" refresh address register:
Bit(s)	Description	(Table P0244)
 7-0	during buffered DMA cycle reflected on bits 23-16 of SA lines,
	  bits 15-10 of SA lines cleared
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" GREEN mode control/enable status:
Bit(s)	Description	(Table P0245)
 7	power management SMI# generation enable
 6	GREEN event SMI# generation
	(read)
	0 = GREEN event did not generate SMI#
	1 = GREEN event generated SMI#
	(write)
	0 = disable GREEN event SMI# generation
	1 = enable GREEN event SMI# generation (if bit 7 set)
 5	reload GREEN event timer/wake-up event SMI# generation
	(read)
	0 = wake-up event did not generate SMI#
	1 = wake-up event generated SMI#
	(write)
	0 = disable wake-up event SMI# generation
	1 = enable wake-up event SMI# generation (if bit 7 set)
 4	power management status (read-only)
	0 = NORMAL
	1 = GREEN
 3	power management PPWRL# generation enable
 2	GREEN event PPWRL# generation enable (if bit 3 set)
 1	reload GREEN event timer/wake-up event PPWRL# generation enable
	  (if bit 3 set)
 0	software generation of GREEN event
	0 = no action
	1 = generate GREEN event (if register E1h bit 0 set)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" EPMI control/GREEN event timer:
Bit(s)	Description	(Table P0246)
 7-6	GREEN event timer CLK period
	00 = 119 microseconds
	01 = 12.25 ms
	10 = 1.94 s
	11 = 62.5 s
 5	EPMI0# polarity
	0 = EPMI0# triggered on falling edge
	1 = EPMI0# triggered on rising edge
 4	EPMI0# debounce enable
 3	EPMI0# polarity
	0 = determined by bit 5
	1 = EPMI0# triggered on transition
 2	GREEN event timer time-out GREEN event generation
	(read)
	0 = GREEN event timer time-out did not cause GREEN event
	1 = GREEN event timer time-out did cause GREEN event
	(write)
	0 = disable GREEN event timer time-out GREEN event generation
	1 = enable GREEN event timer time-out GREEN event generation
 1	EPMI0# trigger GREEN event generation
	(read)
	0 = EPMI0# trigger did not cause GREEN event
	1 = EPMI0# trigger did cause GREEN event
	(write)
	0 = disable EPMI0# trigger GREEN event generation
	1 = enable EPMI0# trigger GREEN event generation
 0	software trigger GREEN event generation
	(read)
	0 = software trigger did not cause GREEN event
	1 = software trigger did cause GREEN event
	(write)
	0 = disable software trigger GREEN event generation
	1 = enable software trigger GREEN event generation
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" GREEN event timer initial count register:
Bit(s)	Description	(Table P0247)
 7-0	time-out timer count - 2
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" IRQ event enable register 1:
Bit(s)	Description	(Table P0248)
 7-3	IRQ7-IRQ3 monitoring enable
 2	IRQ15-IRQ0 deglitch enable
 1-0	IRQ1-IRQ0 monitoring enable
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" IRQ event enable register 2:
Bit(s)	Description	(Table P0249)
 7-0	IRQ15-IRQ8 monitoring enable
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" DREQ event enable register:
Bit(s)	Description	(Table P0250)
 7-5	DREQ7-DREQ5 monitoring enable (if register EFh bit 6 set)
 4	reserved
 3-0	DREQ3-DREQ0 monitoring enable (if register EFh bit 6 set)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" device cycle monitor enable register:
Bit(s)	Description	(Table P0251)
 7	programmable IO/MEM monitoring enable
 6	parallel ports monitoring enable
 5	video monitoring enable
 4	hard disk monitoring enable
 3	floppy disk monitoring enable
 2	keyboard monitoring enable
 1	COM1/COM3 monitoring enable
 0	COM2/COM4 monitoring enable
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" wake-up source/programmable IO/memory address:
Bit(s)	Description	(Table P0252)
 7	PREQ# monitoring enable (if register EFh bit 7 set)
 6	LDEV#/DEVSEL# monitoring enable
 5	EPMI0# trigger monitoring enable
 4	reserved
 3	programmable IO/MEM address type
	0 = I/O
	1 = non-system memory
 2-0	programmable IO/MEM address mask bits 2-0 (bit 3 = register FFh bit 0)
	  (mask lowest n bits)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" programmable I/O/MEM address range register:
Bit(s)	Description	(Table P0253)
 7-0	I/O address bits 7-0 or non-system memory address bits 23-16
	  (use register E7h bit 3 to select I/O or non-system memory address)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" programmable I/O/MEM address range register:
Bit(s)	Description	(Table P0254)
 7-0	I/O address bits 15-8 or non-system memory address bits 31-24
	  (use register E7h bit 3 to select I/O or non-system memory address)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" enter GREEN state port register:
Bit(s)	Description	(Table P0255)
 7-0	GREEN state values for external power control latch
	  (transfered to register ECh on enter GREEN state PPWRL#)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" return to NORMAL state configuration port:
Bit(s)	Description	(Table P0256)
 7-0	NORMAL state values for external power control latch
	  (transfered to register ECh on return to NORMAL state PPWRL#)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" shadow register for external power control latch:
Bit(s)	Description	(Table P0257)
 7-0	external power control latch value
	  (write generates PPWRL#)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" device cycle detection enable/status register:
Bit(s)	Description	(Table P0258)
 7	programmed range access SMI# generation
	(read)
	0 = programmed range access did not generate SMI#
	1 = programmed range access generated SMI#
	(write)
	0 = disable programmed range access SMI# generation
	1 = enable programmed range access SMI# generation
 6	LPT access SMI# generation
	(read)
	0 = LPT access did not generate SMI#
	1 = LPT access generated SMI#
	(write)
	0 = disable LPT access SMI# generation
	1 = enable LPT access SMI# generation
 5	video access SMI# generation
	(read)
	0 = video access did not generate SMI#
	1 = video access generated SMI#
	(write)
	0 = disable video access SMI# generation
	1 = enable video access SMI# generation
 4	hard disk access SMI# generation
	(read)
	0 = hard disk access did not generate SMI#
	1 = hard disk access to generated SMI#
	(write)
	0 = disable hard disk access SMI# generation
	1 = enable hard disk access SMI# generation
 3	floppy disk access SMI# generation
	(read)
	0 = floppy disk access did not generate SMI#
	1 = floppy disk access generated SMI#
	(write)
	0 = disable floppy disk access SMI# generation
	1 = enable floppy disk access SMI# generation
 2	keyboard access SMI# generation
	(read)
	0 = keyboard access did not generate SMI#
	1 = keyboard access generated SMI#
	(write)
	0 = disable keyboard access SMI# generation
	1 = enable keyboard access SMI# generation
 1	COM1/COM3 access SMI# generation
	(read)
	0 = COM1/COM3 access did not generate SMI#
	1 = COM1/COM3 access generated SMI#
	(write)
	0 = disable COM1/COM3 access SMI# generation
	1 = enable COM1/COM3 access SMI# generation
 0	COM2/COM4 access SMI# generation
	(read)
	0 = COM2/COM4 access did not generate SMI#
	1 = COM2/COM4 access generated SMI#
	(write)
	0 = disable COM2/COM4 access SMI# generation
	1 = enable COM2/COM4 access SMI# generation
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" STPCLK# modulation register:
Bit(s)	Description	(Table P0259)
 7	CPU STOPCLK state support enable
 6	STOPCLK state CPU hold enable
 5-4	reserved
 3	STPCLK# modulation enable
 2-0	STPCLK# modulation duty cycle; in effect if bit 3 set
	000 = STPCLK# = 1 always (no modulation)
	001 = STPCLK# = 1 for 1/2 period
	010 = STPCLK# = 1 for 1/4 period
	011 = STPCLK# = 1 for 1/8 period
	100 = STPCLK# = 1 for 1/16 period
	101-111 = reserved
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" miscellaneous register:
Bit(s)	Description	(Table P0260)
 7	PREQ# wake-up enable
 6	DREQ# wake-up enable
 5	reserved
 4	GPCS1# and GPCS#2 generation for addresses in registers F4h-F7h enable
 3	reserved
 2	PPWRL# inititiate clock
	0 = 14 MHz
	1 = 33 KHz
 1	timer count read (registers E0h-E2h, EDh, F0h-F2h, FCh-FEh)
	0 = return current value
	1 = return original value
 0	reserved
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" device timer CLK select/enable status register:
Bit(s)	Description	(Table P0261)
 7-6	device timer 1 CLK period
	00 = 119 microseconds
	01 = 12.25 ms
	10 = 1.94 s
	11 = 62.5 s
 5-4	device timer 0 CLK period
	00 = 119 microseconds
	01 = 12.25 ms
	10 = 1.94 s
	11 = 62.5 s
 3	device timer 1 time-out GREEN event generation
	(read)
	0 = device timer 1 time-out did not cause GREEN event
	1 = device timer 1 time-out did cause GREEN event
	(write)
	0 = disable device timer 1 time-out GREEN event generation
	1 = enable device timer 1 time-out GREEN event generation
 2	device timer 0 time-out GREEN event generation
	(read)
	0 = device timer 0 time-out did not cause GREEN event
	1 = device timer 0 time-out did cause GREEN event
	(write)
	0 = disable device timer 0 time-out GREEN event generation
	1 = enable device timer 0 time-out GREEN event generation
 1	device 1 access wake-up event generation
	(read)
	0 = device 1 access did not cause wake-up event
	1 = device 1 access did cause wake-up event
	(write)
	0 = disable device 1 access wake-up event generation
	1 = enable device 1 access wake-up event generation
 0	device 0 access wake-up event generation
	(read)
	0 = device 0 access did not cause wake-up event
	1 = device 0 access did cause wake-up event
	(write)
	0 = disable device 0 access wake-up event generation
	1 = enable device 0 access wake-up event generation
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" device timer IO/MEM select, mask bits register:
Bit(s)	Description	(Table P0262)
 7	device 1 address type
	0 = I/O
	1 = memory
 6-4	device 1 IO/MEM address mask bits 2-0 (bit 3 = register FFh bit 2)
	  (mask lowest n bits)
 3	device 0 address type
	0 = I/O
	1 = memory
 2-0	device 0 IO/MEM address mask bits 2-0 (bit 3 = register FFh bit 2)
	  (mask lowest n bits)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" device 0 IO/MEM address register:
Bit(s)	Description	(Table P0263)
 7-0	I/O address bits 7-0 or memory address bits 23-16
	  (use register F3h bit 3 to select I/O or memory address)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" device 0 IO/MEM address register:
Bit(s)	Description	(Table P0264)
 7-0	I/O address bits 15-8 or memory address bits 31-24
	  (use register F3h bit 3 to select I/O or memory address)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" device 1 IO/MEM address register:
Bit(s)	Description	(Table P0265)
 7-0	I/O address bits 7-0 or memory address bits 23-16
	  (use register F3h bit 7 to select I/O or memory address)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" device 1 IO/MEM address register:
Bit(s)	Description	(Table P0266)
 7-0	I/O address bits 15-8 or memory address bits 31-24
	  (use register F3h bit 7 to select I/O or memory address)
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" power management control register 1:
Bit(s)	Description	(Table P0267)
 7	EPMI1# GREEN event generation
	(read)
	0 = EPMI1# did not cause GREEN event
	1 = EPMI1# caused GREEN event
	(write)
	0 = disable EPMI1# GREEN event generation
	1 = enable EPMI1# GREEN event generation
 6	EPMI1# reload wake-up GREEN state timer enable
 5	EPMI1# polarity
	0 = determined by bit 4
	1 = EPMI1# triggered on transition
 4	EPMI1# polarity
	0 = EPMI1# triggered on falling edge
	1 = EPMI1# triggered on rising edge
 3	EPMI1# debounce enable
 2-0	reserved
Note:	bits 7 and 6 cannot both be set at the same time
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" power management control register 2:
Bit(s)	Description	(Table P0268)
 7	EPMI2# GREEN event generation
	(read)
	0 = EPMI2# did not cause GREEN event
	1 = EPMI2# caused GREEN event
	(write)
	0 = disable EPMI2# GREEN event generation
	1 = enable EPMI2# GREEN event generation
 6	EPMI2# reload wake-up GREEN state timer enable
 5	EPMI2# polarity
	0 = determined by bit 4
	1 = EPMI2# triggered on transition
 4	EPMI2# polarity
	0 = EPMI2# triggered on falling edge
	1 = EPMI2# triggered on rising edge
 3	EPMI2# debounce enable
 2-0	reserved
Note:	bits 7 and 6 cannot both be set at the same time
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" power management control register 3:
Bit(s)	Description	(Table P0269)
 7	EPMI3# GREEN event generation
	(read)
	0 = EPMI3# did not cause GREEN event
	1 = EPMI3# caused GREEN event
	(write)
	0 = disable EPMI3# GREEN event generation
	1 = enable EPMI3# GREEN event generation
 6	EPMI3# reload wake-up GREEN state timer enable
 5	EPMI3# polarity
	0 = determined by bit 4
	1 = EPMI3# triggered on transition
 4	EPMI3# polarity
	0 = EPMI3# triggered on falling edge
	1 = EPMI3# triggered on rising edge
 3	EPMI3# debounce enable
 2-0	reserved
Note:	bits 7 and 6 cannot both be set at the same time
SeeAlso: #P0219

Bitfields for OPTi "Vendetta" general purpose chip select control register:
Bit(s)	Description	(Table P0270)
 7	CPU type
	0 = Intel/AMD
	1 = Cyrix M1
 6	reserved
 5-4	IDE module device ID
	00 = C621h
	01 = D568h
	10 = D768h (ultra DMA)
	11 = reserved
 3	reserved
 2	GPCS2# address bit masking (fourth bit to register F3h bits 6-4)
 1	GPCS1# address bit masking (fourth bit to register F3h bits 2-0)
 0	GPCS0# address bit masking (fourth bit to register E7h bits 2-0)
Note:	indexes ADh and FFh address same register
SeeAlso: #P0219

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P00220025 - PORT 0022-0025 - INTEL 82360SL CHIPSET (FOR 386SL)

PORT 0022-0025 - INTEL 82360SL CHIPSET (FOR 386SL)

0022  -W  CPU write mode register
0023  R-  configuration status register
		bit 7: 82360 configuration is open
0024  -W  82360 configuration index
0025  RW  82360 configuration data

Bitfields for Intel 82360SL CPU write mode register:
Bit(s)	Description	(Table P0271)
 0	unlock configuration space
 1	enable selected unit
 3-2	unit
	00 memory configuration
	01 cache
	10 internal bus
	11 external bus

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P0022002B - PORT 0022-002B - INTEL 82355, PART OF CHIPSET FOR 386sx

PORT 0022-002B - INTEL 82355, PART OF CHIPSET FOR 386sx
Note:	initialisation in POST will disable these addresses, only a hard
	  reset will enable them again.

0022w RW  82335 MCR memory configuration register (if LOCK=0) (see #P0272)
0024w RW  82335 RC1 roll compare register (if LOCK=0) (see #P0273)
0026w RW  82335 RC2 roll compare register (if LOCK=0) (see #P0273)
0028w RW  82335 CC0 address range compare register (if LOCK=0) (see #P0274)
002Aw RW  82335 CC1 address range compare register (if LOCK=0) (see #P0274)

Bitfields for 82335 MCR memory configuration register:
Bit(s)	Description	(Table P0272)
 15-12	reserved
 11	"VRO"	video read only (0=r/w, 1=r/o)
 10	"EN#"
	0=enable video RAM accesses (A0000h-8FFFFh)
	1=disable accesses
 9	"ENADP#"
	0=enable adapter ROM accesses (C0000h-8FFFFh)
	1=disable adapter ROM accesses, shadow enabled
 8	"ROMSIZE" 0=256KB ROM, 1=512KB ROM
 7-6	"INTERL" memory interleaving
	00 = 1 memory bank installed (no interleave)
	01 = 2 memory banks installed
	10 = 3 memory banks installed
	11 = 4 memory banks installed
 5	reserved
 4	"DSIZE"	 0=1MBx1DRAMs, 1=256KBx1 or 256KBx4 DRAMs
 3	"S640"	 base memory size is 0=512KB, 1=640KB
 2-1	reserved
 0	"ROMEN#" ROM enable
	0 enable BIOS ROM accesses (E0000h-FFFFFh)
	1 disable BIOS ROM accesses, enable shadow
Note:	One of the remaining reserved bits is the LOCK bit, which will be set
	  during power on, disabling access to the 82335s registers.

Bitfields for 82335 roll compare register:
Bit(s)	Description	(Table P0273)
 15-9	selects address range to be remapped (C23-C17)
 8	reserved
 7-1	selects address bits to be included in re-mapping comparision (M23-M17)
 0	"EN" enables roll address mapping

Bitfields for 82335 address range compare register:
Bit(s)	Description	(Table P0274)
 15-11	specifies top of address range (C23-C19)
 10-8	reserved
 7-3	selects address bits to be included in address range comparision
	  (M23-M19)
 2-1	reserved
 0	"EN" enable address range comparision

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P00240025 - PORT 0024-0025 - Intel 82091AA Advanced Integrated Peripheral

PORT 0024-0025 - Intel 82091AA Advanced Integrated Peripheral
Range:	PORT 0022h (X-Bus), PORT 0024h (X-Bus), PORT 026Eh (ISA), or
	  PORT 0398h (ISA)
SeeAlso: PORT 0022h"82091AA",PORT 026Eh"82091AA",PORT 0398h"82091AA"

0024  ?W  configuration register index
0025  RW  configuration register data

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P00240026 - PORT 0024-0026 - PicoPower Vesuvius - V3-LS

PORT 0024-0026 - PicoPower Vesuvius - V3-LS
Note:	software must use 8-bit accesses to these ports; 16-bit accesses will
	  be directed to the V1-LS chip in the chipset instead of the V3-LS
SeeAlso: PORT 0024h"V1-LS"

0024b  ?W  V3-LS register index (see #P0275)
0026b  RW  V3-LS register data

(Table P0275)
Values for PicoPower Vesuvius V3-LS register index:
 00h	revision ID register (see #P0276)
 01h	AT control register 1 (see #P0277)
 02h	AT control register 2 (see #P0278)
 03h	BIOS CS# control register (see #P0279)
 05h	port 92h control register (see #P0280)
 06h	GPEXT low byte register (write high byte into register 07h before
	  writing low byte)
 07h	GPEXT high byte register (write high byte before writing low byte into
	  register 06h)
 08h	miscellaneous configuration register (see #P0281)
 10h	PCI interrupt mapping register 1 (see #P0282)
 11h	PCI interrupt mapping register 2 (see #P0283)
 12h	PCI INT# configuration register (see #P0284)
 13h	serial IRQ control register (see #P0285)
 14h	serial IRQ control register 2 (see #P0286)
 20h	power management control register (see #P0287)
 21h	primary activity IRQ mask register 1 (see #P0288)
 22h	primary activity IRQ mask register 2 (see #P0289)
 23h	PMI trigger IRQ mask register 1 (see #P0290)
 24h	PMI trigger IRQ mask register 2 (see #P0291)
 25h	PMI trigger source register 1 (see #P0292)
 26h	PMI trigger source register 2 (see #P0293)
 30h	8254 counter 0 initial count low byte shadow
 31h	8254 counter 0 initial count high byte shadow
 32h	8254 counter 1 initial count low byte shadow
 33h	8254 counter 1 initial count high byte shadow
 34h	8254 counter 2 initial count low byte shadow
 35h	8254 counter 2 initial count high byte shadow
 36h	8254 counter 0 control word shadow
 37h	8254 counter 1 control word shadow
 38h	8254 counter 2 control word shadow
 39h	8237 DMA controller mode register for channel 0 shadow
 3Ah	8237 DMA controller mode register for channel 1 shadow
 3Bh	8237 DMA controller mode register for channel 2 shadow
 3Ch	8237 DMA controller mode register for channel 3 shadow
 3Dh	8237 DMA controller mode register for channel 4 shadow
 3Eh	8237 DMA controller mode register for channel 5 shadow
 3Fh	8237 DMA controller mode register for channel 6 shadow
 40h	8237 DMA controller mode register for channel 7 shadow
 41h	8259 PIC 1 ICW 1 shadow
 42h	8259 PIC 1 ICW 2 shadow
 43h	8259 PIC 1 ICW 3 shadow
 44h	8259 PIC 1 ICW 4 shadow
 45h	8259 PIC 1 OCW 2 shadow
 46h	8259 PIC 1 OCW 3 shadow
 47h	8259 PIC 2 ICW 1 shadow
 48h	8259 PIC 2 ICW 2 shadow
 49h	8259 PIC 2 ICW 3 shadow
 4Ah	8259 PIC 2 ICW 4 shadow
 4Bh	8259 PIC 2 OCW 2 shadow
 4Ch	8259 PIC 2 OCW 3 shadow
 4Dh	RTC index register shadow
 4Eh	reserved
 4Fh	fixed disk register (port 3F6h) shadow
 50h	hard disk write precompression register (port 1F1h) shadow
 51h	DMA controller 1 status register shadow
 52h	DMA controller 2 status register shadow
 53h	DMAC mask register shadow
 54h	DMA channel 0 base address low byte shadow
 55h	DMA channel 0 base address high byte shadow
 56h	DMA channel 0 base count low byte shadow
 57h	DMA channel 0 base count high byte shadow
 58h	DMA channel 1 base address low byte shadow
 59h	DMA channel 1 base address high byte shadow
 5Ah	DMA channel 1 base count low byte shadow
 5Bh	DMA channel 1 base count high byte shadow
 5Ch	DMA channel 2 base address low byte shadow
 5Dh	DMA channel 2 base address high byte shadow
 5Eh	DMA channel 2 base count low byte shadow
 5Fh	DMA channel 2 base count high byte shadow
 60h	DMA channel 3 base address low byte shadow
 61h	DMA channel 3 base address high byte shadow
 62h	DMA channel 3 base count low byte shadow
 63h	DMA channel 3 base count high byte shadow
 64h	DMA channel 5 base address low byte shadow
 65h	DMA channel 5 base address high byte shadow
 66h	DMA channel 5 base count low byte shadow
 67h	DMA channel 5 base count high byte shadow
 68h	DMA channel 6 base address low byte shadow
 69h	DMA channel 6 base address high byte shadow
 6Ah	DMA channel 6 base count low byte shadow
 6Bh	DMA channel 6 base count high byte shadow
 6Ch	DMA channel 7 base address low byte shadow
 6Dh	DMA channel 7 base address high byte shadow
 6Eh	DMA channel 7 base count low byte shadow
 6Fh	DMA channel 7 base count high byte shadow
 70h	DMA controller 1 command register shadow
 71h	DMA controller 2 command register shadow
Note:	shadow registers (30h-71h) are read-only
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V3-LS revision ID register:
Bit(s)	Description	(Table P0276)
 7-4	V3-LS revision ID
	1h = revision A
	2h = revision B
	3h = revision C
 3-0	V3-LS metal-mask version ID
	0h = version A
	1h = version B
	3h = version C
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS AT control register 1:
Bit(s)	Description	(Table P0277)
 7-6	(revision BB and later) back-to-back delay for 8-bit I/O cycle
	00 = 0.5 SYSCLKs
	01 = 2.5 SYSCLKs
	10 = 4.5 SYSCLKs
	11 = 6.5 SYSCLKs
 5-4	(revision BB and later) back-to-back delay for 16-bit I/O cycle
	00 = 0.5 SYSCLKs
	01 = 1.5 SYSCLKs
	10 = 2.5 SYSCLKs
	11 = 3.5 SYSCLKs
 3	reserved
 2-0	SYSCLK divisor select
	000 = BSERCLK/2
	001 = BSERCLK/3
	010 = BSERCLK/4
	011 = BSERCLK/5
	100 = BSERCLK/6
	101-110 = reserved
	111 = 14MHZCLK/2
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS AT control register 2:
Bit(s)	Description	(Table P0278)
 7	reserved
 6	(revision BB and later) external keyboard chip select
	0 = ROM_KBCS# decodes ports 60h/64h as keyboard ports
	1 = ROM_KBCS# decodes ports 60h/62h/64h/66h as keyboard ports
 5-4	reserved
 3	(revision BB and later) EISA type CMOS RAM interface control enable
 2	(revision BB and later) V3-LS internal I/O port option
	0 = normal V3-LS internal I/O port access
	1 = speed up V3-LS internal I/O port access
 1	extended AT address
 0	AT bus refresh enable
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS BIOS CS# control register:
Bit(s)	Description	(Table P0279)
 7	reserved
 6	flash enable
 5	E8000h-EFFFFh ROMCS# enable
 4	E0000h-E7FFFh ROMCS# enable
 3	D8000h-DFFFFh ROMCS# enable
 2	D0000h-D7FFFh ROMCS# enable
 1	C8000h-CFFFFh ROMCS# enable
 0	C0000h-C7FFFh ROMCS# enable
Notes:	FE000000h-FFFFFFFFh access always generates ROMCS#
	F0000h-FFFFFh access generates ROMCS# if not shadowed
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS port 92h control register:
Bit(s)	Description	(Table P0280)
 7-2	reserved
 1	security lock 1 (port 92h bit 3) function enable
 0	port 92h enable
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS miscellaneous configuration register:
Bit(s)	Description	(Table P0281)
 7	reserved
 6	reserved (ISA master I/O command synchronizer disable)
 5	reserved (timer synchronous IOW# fix disable)
 4	reserved
 3	(revision BB and later) DDMA grant
	0 = V3-LS uses REQ#/GNT# for DDMA retry cycle
	1 = V3-LS does not use REQ#/GNT# for DDMA retry cycle
 2	BSER interrupt enable
 1	(revision BB and later) DDMARETRY
	0 = pin 44 (176-pin) / pin 48 (208-pin) is DDMA_RETRY
	1 = pin 44 (176-pin) / pin 48 (208-pin) is ISA_WAKE
 0	BSER arbitration enable
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS PCI interrupt mapping register 1:
Bit(s)	Description	(Table P0282)
 7-4	map INTB# to IRQ
	0000 = disabled
	0001-0010 = reserved
	0011-0111 = IRQ3-IRQ7
	1000 = reserved
	1001-1100 = IRQ9-IRQ12
	1101 = reserved
	1110-1111 = IRQ14-IRQ15
 3-0	map INTA# to IRQ (same values as bits 7-4)
SeeAlso: #P0275,#P0283

Bitfields for PicoPower Vesuvius V3-LS PCI interrupt mapping register 2:
Bit(s)	Description	(Table P0283)
 7-4	map INTD# to IRQ
	0000 = disabled
	0001-0010 = reserved
	0011-0111 = IRQ3-IRQ7
	1000 = reserved
	1001-1100 = IRQ9-IRQ12
	1101 = reserved
	1110-1111 = IRQ14-IRQ15
 3-0	map INTC# to IRQ (same values as bits 7-4)
SeeAlso: #P0275,#P0282,#P0284

Bitfields for PicoPower Vesuvius V3-LS PCI INT# configuration register:
Bit(s)	Description	(Table P0284)
 7-4	reserved
 3	interrupt D / mappable IRQ 3 configuration
	0 = INTD#, go through level-to-edge conversion
	1 = MIRQ3, bypass level-to-edge conversion
 2	interrupt C / mappable IRQ 2 configuration
	0 = INTC#, go through level-to-edge conversion
	1 = MIRQ2, bypass level-to-edge conversion
 1	interrupt B / mappable IRQ 1 configuration
	0 = INTB#, go through level-to-edge conversion
	1 = MIRQ1, bypass level-to-edge conversion
 0	interrupt A / mappable IRQ 0 configuration
	0 = INTA#, go through level-to-edge conversion
	1 = MIRQ0, bypass level-to-edge conversion
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS serial IRQ control register:
Bit(s)	Description	(Table P0285)
 7	reserved
 6	serial IRQ mode
	0 = host (primary V3-LS)
	1 = source (secondary V3-LS)
 5-4	reserved
 3-2	start cycle length = 2N+4 clocks
 1	host poll
 0	serial IRQ bus enable
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS serial IRQ control register 2:
Bit(s)	Description	(Table P0286)
 7-4	reserved
 3-0	(revision BB and later) serial IRQ sampling slot length
	1111 = 32 slots
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS power management control register:
Bit(s)	Description	(Table P0287)
 7	secondary activity triggered by IRQ1 (write 0 to clear)
 6	secondary activity triggered by IRQ0 (write 0 to clear)
 5	mask IRQ1 from secondary activity
 4	mask IRQ0 from secondary activity
 3	(revision BB and later) IMR disable
 2	primary activity enables PMI
 1	reserved
 0	burst serial bus enable
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS primary activity IRQ mask register 1:
Bit(s)	Description	(Table P0288)
 7-3	mask IRQ7 - IRQ3 from primary activity
 2	mask NMI from primary activity
 1	mask IRQ1 from primary activity
 0	reserved
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS primary activity IRQ mask register 2:
Bit(s)	Description	(Table P0289)
 7-1	mask IRQ15 - IRQ9 from primary activity
 0	mask IRQ8 from primary activity
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS PMI trigger IRQ mask register 1:
Bit(s)	Description	(Table P0290)
 7-3	mask IRQ7 - IRQ3 from PMI
 2	reserved
 1	mask IRQ1 from PMI
 0	mask DDMA slave lock from PMI
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS PMI trigger IRQ mask register 2:
Bit(s)	Description	(Table P0291)
 7-1	mask IRQ15 - IRQ9 from PMI
 0	mask IRQ8 from PMI
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS PMI trigger source register 1:
Bit(s)	Description	(Table P0292)
 7-3	PMI trigger source IRQ7 - IRQ3 active (write 0 to clear)
 2	reserved
 1	PMI trigger source IRQ1 active (write 0 to clear)
 0	PMI trigger source DDMA slave lock active (write 0 to clear)
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V3-LS PMI trigger source register 2:
Bit(s)	Description	(Table P0293)
 7-1	PMI trigger source IRQ15 - IRQ9 active (write 0 to clear)
 0	PMI trigger source IRQ8 active (write 0 to clear)
SeeAlso: #P0275

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P00240027 - PORT 0024-0027 - PicoPower Vesuvius - V1-LS

PORT 0024-0027 - PicoPower Vesuvius - V1-LS
Note:	software must use 16-bit accesses to these ports; 8-bit accesses will
	  be directed to the V3-LS chip in the chipset instead of the V1-LS
SeeAlso: PORT 0024h"V3-LS"

0024w  ?W  V1-LS register index (see #P0294)
0026w  RW  V1-LS register data

(Table P0294)
Values for PicoPower Vesuvius V1-LS register index:
 01xxh	(reset sampling and miscellaneous)
 0100h	revision ID register (see #P0295)
 0101h	V1 power on register (see #P0296)
 0108h	V2 version ID register (see #P0297)
 0109h	V2 configuration register (see #P0298)
 010Ah	V2 miscellaneous status register (see #P0299)
 0110h	programmable region 1 register (see #P0300)
 0111h	programmable region 2 register (see #P0300)
 0112h	programmable region 3 register (see #P0300)
 0113h	programmable region 4 register (see #P0300)
 0114h	programmable region control register (see #P0301)
 0118h	SMM control register (see #P0302)
 0119h	processor control register (see #P0303)
 011Ah	write FIFO control register (see #P0304)
 011Bh	PCI control register (see #P0305)
 011Ch	clock skew adjust register (see #P0306)
 011Dh	bus master and snooping control register (see #P0307)
 011Eh	arbiter control register (see #P0308)
 011Fh	docking control register (see #P0309)
 02xxh	(DRAM registers)
 0200h	shadow RAM read enable control register (see #P0310)
 0201h	shadow RAM write enable control register (see #P0311)
 0202h	bank 0 control register (see #P0312)
 0203h	bank 1 control register (see #P0312)
 0204h	bank 0/1 timing control register (see #P0313)
 0205h	bank 2 control register (see #P0312)
 0206h	bank 3 control register (see #P0312)
 0207h	bank 2/3 timing control register (see #P0313)
 0208h	bank 4 control register (see #P0312)
 0209h	bank 5 control register (see #P0312)
 020Ah	bank 4/5 timing control register (see #P0313)
 020Bh	bank 6 control register (see #P0312)
 020Ch	bank 7 control register (see #P0312)
 020Dh	bank 6/7 timing control register (see #P0313)
 020Eh	DRAM configuration register 1 (see #P0314)
 020Fh	DRAM configuration register 2 (see #P0315)
 0210h	DRAM configuration register 3 (see #P0316)
 0211h	DRAM refresh control register (see #P0317)
 0212h	burst EDO control register (see #P0318)
 03xxh	(Power Management control)
 0300h	clock control register (see #P0319)
 0301h	clock throttling period control register (see #P0320)
 0302h	conserve clock throttling ratio/control register (see #P0321)
 0303h	heat regulator clock throttling ratio/control register (see #P0322)
 0304h	doze/sleep mode clock throttling ratio/control register (see #P0323)
 0310h	wake/SMI source register (see #P0324)
 0311h	power management timer status register (see #P0326)
 0312h	power management pin status register (see #P0327)
 0313h	wake mask control register (see #P0328)
 0314h	activity flag register 1 (see #P0329)
 0315h	activity flag register 2 (see #P0330)
 0316h	I/O trap SMI mask register (see #P0331)
 0317h	external SMI trigger mask register (see #P0332)
 0318h	internal SMI trigger mask register (see #P0333)
 0319h	software SMI trigger mask register (see #P0334)
 031Ah	primary activity option control register (see #P0335)
 031Bh	primary activity mask register 1 (see #P0336)
 031Ch	primary activity mask register 2 (see #P0337)
 031Dh	secondary activity mask register (see #P0338)
 031Eh	RING count control register (see #P0339)
 0320h	programmable range monitor control register 1 (see #P0340)
 0321h	programmable range monitor control register 2 (see #P0341)
 0322h	programmable range monitor 0 address register (see #P0342)
 0323h	programmable range monitor 0 compare register (see #P0343)
 0324h	programmable range monitor 1 address register (see #P0342)
 0325h	programmable range monitor 1 compare register (see #P0343)
 0326h	programmable range monitor 2 address register (see #P0342)
 0327h	programmable range monitor 2 compare register (see #P0343)
 0328h	programmable range monitor 3 address register (see #P0342)
 0329h	programmable range monitor 3 compare register (see #P0343)
 032Ah	programmable range monitor 4 address register (see #P0342)
 032Bh	programmable range monitor 4 compare register (see #P0343)
 032Ch	programmable range monitor 5 address register (see #P0342)
 032Dh	programmable range monitor 5 compare register (see #P0343)
 0330h	power management mode register (see #P0344)
 0331h	on/doze mode power control register (see #P0345)
 0332h	sleep mode power control register (see #P0346)
 0333h	suspend mode power control register (see #P0347)
 0335h	doze mode timer register (see #P0348)
 0336h	sleep mode timer register (see #P0349)
 0337h	suspend mode timer register (see #P0349)
 0338h	secondary activity timer register (see #P0350)
 0339h	power on demand primary activity timer register (see #P0351)
 0340h	general purpose control register (see #P0352)
 0341h	general purpose counter/timer control register (see #P0353)
 0342h	general purpose counter/timer current value register (see #P0354)
 0343h	general purpose counter/timer compare register (see #P0355)
 0344h	device timer 0 time-out register (see #P0356)
 0345h	device timer 1 time-out register (see #P0356)
 0346h	device timer 2 time-out register (see #P0356)
 0347h	device timer 3 time-out register (see #P0356)
 0348h	device timer 4 time-out register (see #P0356)
 0349h	device timer 5 time-out register (see #P0356)
 034Ah	device timer time-out source register 1 (see #P0357)
 034Bh	device timer time-out source register 2 (see #P0358)
 034Ch	device timer time-out source register 3 (see #P0359)
 034Dh	device timer time-out source register 4 (see #P0360)
 0350h	LED indicator control register (see #P0361)
 0351h	leakage control register (see #P0362)
 0352h	pin multiplexing control register (see #P0363)
 0353h	debounce control register (see #P0364)
 0354h	edge detect control register (see #P0365)
 04xxh	(Level-2 Cache)
 0400h	L2 cache configuration register (see #P0366)
 0401h	L2 cache timing register (see #P0367)
 0402h	L2 cache miscellaneous register (see #P0368)
SeeAlso: #P0275

Bitfields for PicoPower Vesuvius V1-LS revision ID register:
Bit(s)	Description	(Table P0295)
 15-4	reserved
 3-0	V1-LS metal-mask version ID
	3h = revision AA
	4h = revision BB
	5h = revision CC
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS V1 power on register:
Bit(s)	Description	(Table P0296)
 15-12	reserved
 11	use internal clocks for simulation
	0 = internal clock speedup disabled
	0 = internal clock speedup enabled
 10	tristate all outputs
	0 = no tristate condition
	1 = tristate condition
 9	reserved
 8	(revision CC and later) snooping scheme
	0 = HOLD/HLDA
	1 = BOFF#/LOCK#
 7	(revision BB and later) PCI power plane voltage
	0 = 3.3 V
	1 = 5 V
 6	(revision BB and later) DRAM power plane voltage
	0 = 3.3 V
	1 = 5 V
 5-3	clock skew adjust
	000 = 0.0 ns
	001 = +0.55 ns
	010 = +1.10 ns
	011 = +1.65 ns
	100 = -2.20 ns
	101 = -1.65 ns
	110 = -1.10 ns
	111 = -0.55 ns
 2-0	miscellaneous configuration
Note:	this register is read-only
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V2-LS V2 version ID register:
Bit(s)	Description	(Table P0297)
 15-12	reserved
 11-8	V2-LS version ID (even)
	3h = revision AA
	4h = revision BB
 7-4	reserved
 3-0	V2-LS version ID (odd) (same values as bits 11-8)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V2-LS V2 configuration register:
Bit(s)	Description	(Table P0298)
 15	V2-LS process monitor enable (odd)
 14-9	reserved
 8	fast PCI master address transfer enable (odd)
 7	V2-LS process monitor enable (even)
 6-1	reserved
 0	fast PCI master address transfer enable (even)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V2-LS V2 miscellaneous status register:
Bit(s)	Description	(Table P0299)
 15-10	reserved
 9	(revision BB & later) PCI power plane voltage (odd)
	0 = 3.3 V
	1 = 5 V
 8	(revision BB & later) DRAM power plane voltage (odd) (as for bit 9)
 7-2	reserved
 1	(revision BB & later) PCI power plane voltage (even) (as for bit 9)
 0	(revision BB & later) DRAM power plane voltage (even) (as for bit 9)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS programmable region register:
Bit(s)	Description	(Table P0300)
 15-3	programmable region starting address bits 27-15 (bits 31-28 = 0)
	(starting address must be a multiple of block size)
 2-0	programmable region block size
	000 = 32 KB
	001 = 64 KB
	010 = 128 KB
	011 = 256 KB
	100 = 512 KB
	101 = 1 MB
	110-111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS programmable region control register:
Bit(s)	Description	(Table P0301)
 15-8	reserved
 7-6	programmable region 4 select
	00 = disable
	01 = write-through
	10 = non-cacheable
	11 = reserved
 5-4	programmable region 3 select (same values as bits 7-6)
 3-2	programmable region 2 select (same values as bits 7-6)
 1-0	programmable region 1 select (same values as bits 7-6)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS SMM control register:
Bit(s)	Description	(Table P0302)
 15	SMM RAM access in normal mode lock (can only be written once)
	0 = bit 14 not locked
	1 = bit 14 locked to disabled
 14	load SMI handler into SMM RAM
	0 = access to SMM RAM during normal cycle disabled
	1 = access to SMM RAM during normal cycle enabled
 13	(revision BB and later) swap SMM D/E mapping
	0 = D0000h-DFFFFh mapped to A0000h-AFFFFh and E0000h-EFFFFh mapped to
	  B0000h-BFFFFh
	1 = D0000h-DFFFFh mapped to B0000h-BFFFFh and E0000h-EFFFFh mapped to
	  A0000h-AFFFFh
 12	(revision BB and later) swap SMM 2/3 mapping
	0 = 20000h-2FFFFh mapped to A0000h-AFFFFh and 30000h-3FFFFh mapped to
	  B0000h-BFFFFh
	1 = 20000h-2FFFFh mapped to B0000h-BFFFFh and 30000h-3FFFFh mapped to
	  A0000h-AFFFFh
 11-10	SMM E8000h-EFFFFh select
	00 = normal memory space
	01 = reserved
	10 = SMM space (remap to B8000h-BFFFFh; E8000h-EFFFFh automatically set
	  to non-cacheable)
	11 = reserved
 9-8	SMM E0000h-E7FFFh select
	00 = normal memory space
	01 = reserved
	10 = SMM space (remap to B0000h-B7FFFh; E0000h-E7FFFh automatically set
	  to non-cacheable)
	11 = reserved
 7-6	SMM D8000h-DFFFFh select
	00 = normal memory space
	01 = reserved
	10 = SMM space (remap to A8000h-AFFFFh; D8000h-DFFFFh automatically set
	  to non-cacheable)
	11 = reserved
 5-4	SMM D0000h-D7FFFh select
	00 = normal memory space
	01 = reserved
	10 = SMM space (remap to A0000h-A7FFFh; D0000h-D7FFFh automatically set
	  to non-cacheable)
	11 = reserved
 3	reserved
 2	20000h-3FFFFh remap to A0000h-BFFFFh in SMM mode disable
	(can be used only when L1 and L2 are disabled)
 1	SMRAM KEN disable
 0	reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS processor control register:
Bit(s)	Description	(Table P0303)
 15-10	reserved
 9	FPU error clearing by writing to I/O port F1h disable
 8	FPU error clearing by writing to I/O port F0h disable
 7	reserved
 6	assert INV for write cycle only
 5	write FIFO
	0 = disabled (FIFO forced to one level)
	1 = enabled (FIFO forced to eight level)
 4	combine KEN# and INV pins
 3	linear burst enable
 2	processor pipeline mode enable
 1	L1 write-back enable
 0	CACHE enable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS write FIFO control register:
Bit(s)	Description	(Table P0304)
 15-7	reserved
 6-5	PCI write buffering select
	00 = disable
	01 = post-write PCI IO write cycle only
	10 = post-write PCI memory write cycle only
	11 = post-write all PCI write cycles
 4	(revision BB and later) PCI read reordering enable
 3	(revision BB and later) DRAM read reordering enable
 2-0	reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS PCI control register:
Bit(s)	Description	(Table P0305)
 15-4	reserved
 3	optimized address transfer between V1-LS and V2-LS enable
 2	reserved
 1	PCI master-to-DRAM burst enable
 0	reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS clock skew adjust register:
Bit(s)	Description	(Table P0306)
 15-3	reserved
 2-0	L2CLK skew adjust
	000 = 0.0 ns
	001 = +0.55 ns
	010 = +1.10 ns
	011 = +1.65 ns
	100 = -2.20 ns
	101 = -1.65 ns
	110 = -1.10 ns
	111 = -0.55 ns
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS bus master and snooping control register:
Bit(s)	Description	(Table P0307)
 15-14	reserved
 13	early DRAM cycle when PCI master accessing DRAM disable
 12-0	reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS arbiter control register:
Bit(s)	Description	(Table P0308)
 15-7	reserved
 6	REQ2# as FLOAT_REQ# and GNT2# as FLOAT_GNT# enable
 5-4	SIO request/grant source
	00 = none
	01 = BSER interface (normal operation)
	10-11 = reserved
 3	preemptability of PCI request/grant 3 disable
 2	preemptability of PCI request/grant 2 disable
 1	preemptability of PCI request/grant 1 disable
 0	preemptability of PCI request/grant 0 disable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS docking control register:
Bit(s)	Description	(Table P0309)
 15	system docked
 14-4	reserved
 3	DOCK_PCICLK follows state of PCICLK enable
 2	deassert DOCK_PCIRST#
 1	reserved
 0	tristate DOCK_PCIRST# and DOCK_PCICLK in normal operating mode enable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS shadow RAM read enable control register:
Bit(s)	Description	(Table P0310)
 15	local memory FC000h-FFFFFh read enable
 14	local memory F8000h-FBFFFh read enable
 13	local memory F4000h-F7FFFh read enable
 12	local memory F0000h-F3FFFh read enable
 11	local memory EC000h-EFFFFh read enable
 10	local memory E8000h-EBFFFh read enable
 9	local memory E4000h-E7FFFh read enable
 8	local memory E0000h-E3FFFh read enable
 7-4	local memory Dx000h-DyFFFh read enable
	  (x/y = 0/3 for bit 4, 4/7 for bit 5, etc.)
 3-0	local memory Cx000h-CyFFFh read enable
	  (x/y = 0/3 for bit 0, 4/7 for bit 1, etc.)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS shadow RAM write enable control:
Bit(s)	Description	(Table P0311)
 15	local memory FC000h-FFFFFh write enable
 14	local memory F8000h-FBFFFh write enable
 13	local memory F4000h-F7FFFh write enable
 12	local memory F0000h-F3FFFh write enable
 11	local memory EC000h-EFFFFh write enable
 10	local memory E8000h-EBFFFh write enable
 9	local memory E4000h-E7FFFh write enable
 8	local memory E0000h-E3FFFh write enable
 7-4	local memory Dx000h-DyFFFh write enable
	  (x/y = 0/3 for bit 4, 4/7 for bit 5, etc.)
 3-0	local memory Cx000h-CyFFFh write enable
	  (x/y = 0/3 for bit 0, 4/7 for bit 1, etc.)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS bank control register:
Bit(s)	Description	(Table P0312)
 15	reserved
 14-12	number of column address bits for bank
	000 = 8 bits
	001 = 9 bits
	010 = 10 bits
	011 = 11 bits
	100 = 12 bits
	101-111 = reserved
 11-9	bank DRAM size
	000 = 1 MB
	001 = 2 MB
	010 = 4 MB
	011 = 8 MB
	100 = 16 MB
	101 = 32 MB
	110 = 64 MB
	111 = reserved
 8	reserved
 7-0	bank starting address bits 27-20
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS bank timing control register:
Bit(s)	Description	(Table P0313)
 15-14	reserved
 13-12	bank 0/2/4/6 and 1/3/5/7 CAS write pulse width
	00 = 0.5T (EDO or burst EDO only)
	01 = 1.0T
	10 = 1.5T
	11 = 2.0T
 11-9	bank 0/2/4/6 and 1/3/5/7 CAS read pulse width
	000 = 0.5T (EDO or burst EDO only)
	001 = 1.0T
	...
	111 = 4.0T
 8	bank 0/2/4/6 and 1/3/5/7 CAS precharge time
	0 = 0.5T
	1 = 1.0T
 7	bank 0/2/4/6 and 1/3/5/7 CAS address hold time (same values as bit 8)
 6-5	bank 0/2/4/6 and 1/3/5/7 RAS address setup time
	00 = 0.0T
	01 = 0.5T
	10 = 1.0T
	11 = 1.5T
 4-3	bank 0/2/4/6 and 1/3/5/7 RAS address hold time = N/2 + 0.5T
 2-0	bank 0/2/4/6 and 1/3/5/7 RAS precharge time    = N/2 + 1.5T
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS DRAM configuration register 1:
Bit(s)	Description	(Table P0314)
 15-9	reserved
 8	fast cacheless read enable (L2 must be disabled and L2 read lead-off
	  must be 2T)
 7-6	DRAM auto-detect mode
	00 = normal mode
	01 = setup for auto-detect
	10 = reserved
	11 = auto-detect read mode
 5-3	DRAM inactive time-out
	000 = never
	001 = 8 T
	010 = 32 T
	011 = 128 T
	100 = 512 T
	101-110 = reserved
	111 = immediate
 2-0	reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS DRAM configuration register 2:
Bit(s)	Description	(Table P0315)
 15-12	reserved
 11	banks 6 and 7
	0 = two 32-bit banks
	1 = one 64-bit bank (bits 7-6 ignored; bank 6 DRAM parameters used;
	  programmed bank 6 size doubled)
 10	banks 4 and 5 (same settings as for bit 11)
 9	banks 2 and 3 (same settings as for bit 11)
 8	banks 0 and 1
	0 = two 32-bit banks
	1 = one 64-bit bank (bits 1-0 ignored; bank 0 DRAM parameters used;
	  programmed bank 0 size doubled)
 7-0	corresponding bank enable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS DRAM configuration register 3:
Bit(s)	Description	(Table P0316)
 15-14	bank 7 DRAM type
	00 = standard
	01 = EDO
	10 = burst EDO
	11 = reserved
 13-12	bank 6 DRAM type (same values as bits 15-14)
 11-10	bank 5 DRAM type (same values as bits 15-14)
 9-8	bank 4 DRAM type (same values as bits 15-14)
 7-6	bank 3 DRAM type (same values as bits 15-14)
 5-4	bank 2 DRAM type (same values as bits 15-14)
 3-2	bank 1 DRAM type (same values as bits 15-14)
 1-0	bank 0 DRAM type (same values as bits 15-14)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS DRAM refresh control register:
Bit(s)	Description	(Table P0317)
 15-14	reserved
 13-12	refresh stagger select
	00 = no staggering
	01 = reserved
	10 = stagger active edge of RAS
	11 = stagger both edges of RAS
 11	reserved
 10	suspend mode self-refresh enable
 9-8	reserved
 7-5	refresh period
	000 = 3.75 æs
	001 = 7.5 æs
	010 = 15 æs
	011 = 30 æs
	100 = 120 æs
	101 = stopped
	110-111 = reserved
 4-3	RAS pulse width for refresh cycles
	00 = 6T
	01 = 5T
	10 = 4T
	11 = 3T
 2-1	RAS precharge time for refresh cycles
	00 = 5T
	01 = 4T
	10 = 3T
	11 = 2T
 0	DRAM refresh scheme
	0 = CAS-before-RAS
	1 = RAS-only
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS burst EDO control register:
Bit(s)	Description	(Table P0318)
 15-4	MA setting during write CAS-before-RAS cycle
 3	trigger write CAS-before-RAS configuration cycle
 2-1	DRAM bank configuration select
	00 = bank 0/1
	01 = bank 2/3
	10 = bank 4/5
	11 = bank 6/7
 0	burst EDO write CAS-before-RAS configuration cycle enable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS clock control register:
Bit(s)	Description	(Table P0319)
 15	modular clocking on V2 clock enable
 14-12	reserved
 11	PCI clock control CLKRUN# method enable
 10	reserved
 9	PCI clock goes back to full speed on PCI LOCK# enable
 8	PCI clock goes back to full speed on PCI request/grant enable
 7-6	reserved
 5-4	PCI idle count (PCI clocks)
	00 = immediate
	01 = 8
	10 = 32
	11 = 256
 3-2	reserved
 1-0	PCI clock divisor during idle
	00 = 1
	01 = 2
	10 = 32
	11 = 256
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS clock throttling period control:
Bit(s)	Description	(Table P0320)
 15-3	reserved
 2-0	clock throttling period select (T = CPU bus frequency period)
	000 = 800T
	001 = 1600T
	010 = 3200T
	011 = 6400T
	100 = 12800T
	101 = 25600T
	110 = 102400T
	111 = 409600T
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS conserve clock throttling ratio/control register:
Bit(s)	Description	(Table P0321)
 15-5	reserved
 4	conserve clock throttling enable
 3-0	conserve clock throttling ratio
	0000 = 5% duty cycle
	0001-1001 = 10%-90% duty cycle
	1010-1111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS heat regulator clock throttling:
Bit(s)	Description	(Table P0322)
 15-13	reserved
 12	THERM input enable
 11-4	reserved
 3-0	heat regulator clock throttling ratio
	0000 = 5% duty cycle
	0001-1001 = 10%-90% duty cycle
	1010-1111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS doze/sleep mode clock throttling:
Bit(s)	Description	(Table P0323)
 15-11	reserved
 10-8	STPCLK release latency (PLL stabilization delay)
	000 = 0 s
	001 = 1 æs
	010 = 45 æs
	011 = 1 ms
	100 = 2 ms
	101-111 = reserved
 7-5	sleep mode clock throttling enable
	000 = disable
	001 = enable in ratio set in bits 3-0
	010 = enable LessStop mode (CPU stop grant state)
	011 = enable MoreStop mode (CPU stop clock state)
	100 = enable Deep Sleep mode (MoreStop and high speed oscillator off,
	  only 32 kHz running)
 4	doze mode clock throttling enable
 3-0	doze/sleep mode clock throttling ratio
	0000 = 5% duty cycle
	0001-1001 = 10%-90% duty cycle
	1010-1111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS wake/SMI source register:
Bit(s)	Description	(Table P0324)
 15-11	reserved
 10-8	wake-up source
	000 = none
	001 = RING
	010 = SWTCH
	011 = GP timer compare
	100 = WAKE0
	101 = WAKE1
	110 = reserved
	111 = clear wake-up source (write to clear)
 7-5	reserved
 4-0	SMI source (see #00671)
SeeAlso: #P0294

(Table P0325)
Values for PicoPower Vesuvius V1-LS SMI source:
 00h	none
 01h	primary activity
 02h	I/O trap
 03h	device timer time-out
 04h	doze time-out
 05h	sleep time-out
 06h	suspend time-out
 07h	GP timer compare
 08h	SWTCH input toggling
 09h	reserved
 0Ah	WAKE0 input toggling
 0Bh	WAKE1 input toggling
 0Ch	EXTACT0 toggling
 0Dh	reserved
 0Eh	rescheduled SMI
 0Fh	software SMI
 10h	V3-LS INT SMI
 11h-1Eh reserved
 1Fh	clear SMI source (write to clear)
SeeAlso: #P0324

Bitfields for PicoPower Vesuvius V1-LS power management timer status register:
Bit(s)	Description	(Table P0326)
 15-3	reserved
 2	suspend time-out status (write 0 to clear)
 1	sleep time-out status (write 0 to clear)
 0	doze time-out status (write 0 to clear)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS power management pin status register:
Bit(s)	Description	(Table P0327)
 15-6	reserved
 5	SWTCH pin status (read-only)
 4	RING pin status (read-only)
 3	reserved
 2	EXTACT0 pin status (read-only)
 1	WAKE1 pin status (read-only)
 0	WAKE0 pin status (read-only)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS wake mask control register:
Bit(s)	Description	(Table P0328)
 15-5	reserved
 4	mask GP timer compare from resume
 3	mask RING from resume
 2	mask SWTCH from resume
 1	mask WAKE1 from resume
 0	mask WAKE0 from resume
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS activity flag register 1:
Bit(s)	Description	(Table P0329)
 15-10	programmable range 5-0 monitor active (write 0 to clear)
 9	reserved
 8	HOLD active (write 0 to clear)
 7	parallel I/O active (write 0 to clear)
 6	serial I/O 2 active (write 0 to clear)
 5	serial I/O 1 active (write 0 to clear)
 4	keyboard active (write 0 to clear)
 3	floppy disk active (write 0 to clear)
 2	hard disk 2 active (write 0 to clear)
 1	hard disk 1 active (write 0 to clear)
 0	video active (write 0 to clear)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS activity flag register 2:
Bit(s)	Description	(Table P0330)
 15-14	reserved
 13-8	device timer 5-0 time-out (write 0 to clear)
 7	FLOAT_REQ# active (write 0 to clear)
 6	EXTACT0 active (write 0 to clear)
 5	WAKE1 active (write 0 to clear)
 4	WAKE0 active (write 0 to clear)
 3	SWTCH active (write 0 to clear)
 2	RING active (write 0 to clear)
 1	reserved
 0	V3-LS active (write 0 to clear)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS I/O trap SMI mask register:
Bit(s)	Description	(Table P0331)
 15-10	programmable range 5-0 device on
 9-8	reserved
 7	parallel I/O on
 6	serial I/O 2 on
 5	serial I/O 1 on
 4	keyboard on
 3	floppy disk on
 2	hard disk 2 on
 1	hard disk 1 on
 0	video on
Note:	No group mask for I/O trap.
	SMI generated if a bit is 0 and corresponding device is accessed.
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS external SMI trigger mask register:
Bit(s)	Description	(Table P0332)
 15-4	reserved
 3	mask EXTACT0 from SMI
 2	mask SWTCH from SMI
 1	mask WAKE1 from SMI
 0	mask WAKE0 from SMI
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS internal SMI trigger mask register:
Bit(s)	Description	(Table P0333)
 15-10	reserved
 9	mask GP timer compare from SMI
 8	mask suspend time-out from SMI
 7	mask sleep time-out from SMI
 6	mask doze time-out from SMI
 5-0	mask device timer 5-0 time-out from SMI
Note:	Primary activity mask is in register 31Ah bit 1.
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS software SMI trigger mask register:
Bit(s)	Description	(Table P0334)
 15-10	reserved
 9	soft SMI on I/O write to port B0h enable
 8	soft SMI immediate (write 1 to trigger SMI; read value has no meaning)
 7-5	reserved
 4	reschedule SMI prescalar
	0 = 10 ms
	1 = 100 ms
 3-0	reschedule SMI select
	0000 = disable
	0001-1001 = 1-9
	1010-1111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS primary activity option control:
Bit(s)	Description	(Table P0335)
 15-5	reserved
 4	(revision BB and later) mask SMI from primary activity
 3	primary activity on disable
 2	primary activity latching in SMM mode enable
 1	mask primary activity from SMI
 0	primary activity flag enable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS primary activity mask register 1:
Bit(s)	Description	(Table P0336)
 15-10	primary activity mask programmable range 5-0 accesses
 9	reserved
 8	primary activity mask HOLD
 7	primary activity mask parallel I/O accesses
 6	primary activity mask serial I/O 2 accesses
 5	primary activity mask serial I/O 1 accesses
 4	primary activity mask keyboard accesses
 3	primary activity mask floppy disk accesses
 2	primary activity mask hard disk 2 accesses
 1	primary activity mask hard disk 1 accesses
 0	primary activity mask video accesses
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS primary activity mask register 2:
Bit(s)	Description	(Table P0337)
 15-13	reserved
 12	primary activity mask FLOAT_REQ#
 11	primary activity mask SWTCH
 10	primary activity mask WAKE1
 9	primary activity mask WAKE0
 8	primary activity mask RING
 7	reserved
 6	primary activity mask EXTACT0
 5-0	reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS secondary activity mask register:
Bit(s)	Description	(Table P0338)
 15-7	reserved
 6	mask EXTACT0 from secondary activity
 5-2	reserved
 1	mask HOLD from secondary activity
 0	mask SMI from secondary activity
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS RING count control register:
Bit(s)	Description	(Table P0339)
 15-5	reserved
 4	RINGS ten's digit
	0 = 0
	1 = 1
 3-0	RINGS one's digit
	0000 = disabled (ring counter reset, if bit 4 = 0)
	0001-1001 = 1-9
	1010-1111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS programmable range monitor control 1:
Bit(s)	Description	(Table P0340)
 15-14	reserved
 13-8	programmable range monitor 5-0 enable
 7-6	reserved
 5-0	programmable range monitor 5-0 memory or I/O compare
	0 = I/O
	1 = memory
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS programmable range monitor control 2:
Bit(s)	Description	(Table P0341)
 15-14	reserved
 13-8	programmable range monitor 5-0 read enable
 7-6	reserved
 5-0	programmable range monitor 5-0 write enable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS programmable range monitor address:
Bit(s)	Description	(Table P0342)
 15-0	programmable range monitor address (I/O address bits 15-0; memory
	  address bits 31-16)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS programmable range monitor compare:
Bit(s)	Description	(Table P0343)
 15-0	programmable range monitor compare enable (I/O address bits 15-0;
	  memory address bits 31-16)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS power management mode register:
Bit(s)	Description	(Table P0344)
 15-4	reserved
 3	resume
 2-0	system management mode
	000 = on
	001 = doze
	010 = sleep or deep sleep
	011 = suspend
	100-111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS on/doze mode power control register:
Bit(s)	Description	(Table P0345)
 15-6	reserved
 5-0	power control on/doze mode (if on/doze mode active, 1 means
	  corresponding power control pin is active)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS sleep mode power control register:
Bit(s)	Description	(Table P0346)
 15-6	reserved
 5-0	power control sleep mode (if sleep mode active, 1 means corresponding
	  power control pin is active)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS suspend mode power control register:
Bit(s)	Description	(Table P0347)
 15-6	reserved
 5-0	power control suspend mode (if suspend mode active, 1 means
	  corresponding power control pin is active)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS doze mode timer register:
Bit(s)	Description	(Table P0348)
 15-10	reserved
 9	doze mode timer enable
 8	doze mode timer reset by primary activity enable
 7	doze mode timer clock prescalar
	0 = 100 ms
	1 = 1 s
 6-4	doze mode timer ten's digit
	000-111 = 0-7
 3-0	doze mode timer one's digit
	0000-1001 = 0-9
	1010-1111 = reserved
Note:	the timer is disabled when both ten's and one's digits are 0
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS sleep/suspend mode timer register:
Bit(s)	Description	(Table P0349)
 15-10	reserved
 9	sleep/suspend mode timer enable
 8-7	reserved
 6-4	sleep/suspend mode timer ten's digit (0-7)
 3-0	sleep/suspend mode timer one's digit
	0000-1001 = 0-9
	1010-1111 = reserved
Note:	the timer is disabled when both ten's and one's digits are 0
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS secondary activity timer register:
Bit(s)	Description	(Table P0350)
 15-10	reserved
 9	secondary activity timer enable
 8	reset secondary activity on SMI
 7	secondary activity timer clock prescalar
	0 = 100 æs
	1 = 1 ms
 6-4	secondary activity timer ten's digit (0-7)
 3-0	secondary activity timer one's digit
	0000-1001 = 0-9
	1010-1111 = reserved
Note:	the timer is disabled when both ten's and one's digits are 0
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS power on demand primary activity timer:
Bit(s)	Description	(Table P0351)
 15-10	reserved
 9	primary activity timer enable
 8	reserved
 7	primary activity timer clock prescalar
	0 = 100 æs
	1 = 1 ms
 6-4	primary activity timer ten's digit (0-7)
 3-0	primary activity timer one's digit
	0000-1001 = 0-9
	1010-1111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS general purpose control register:
Bit(s)	Description	(Table P0352)
 15-14	reserved
 13-8	general purpose I/O 5-0 direction
	0 = corresponding GPIO pin is an input
	1 = corresponding GPIO pin is an output
 7-6	reserved
 5-0	general purpose I/O 5-0 data
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS general purpose counter/timer control:
Bit(s)	Description	(Table P0353)
 15-8	reserved
 7	general purpose counter/timer enable
 6-5	general purpose counter/timer select
	     bit 4 = 0	     bit 4 = 1
	00 = 16-bit counter  16-bit counter  (GPIO3 is counter clock)
	01 = 24-bit counter  24-bit counter  (GPIO3 is counter clock)
	10 = 1 second timer  31.25 æs timer
	11 = 1 minute timer  1.875 ms timer
 4	general purpose counter/timer clock select
	0 = 1 Hz
	1 = 32 kHz
 3-0	reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS general purpose counter/timer value:
Bit(s)	Description	(Table P0354)
 15-0	general purpose counter/timer current value (24-bit counter bits
	  23-8, otherwise counter/timer bits 15-0; any write resets
	  counter/timer)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS general purpose counter/timer compare:
Bit(s)	Description	(Table P0355)
 15-0	general purpose counter/timer compare (24-bit counter compare value
	  bits 23-8, otherwise compare value bits 15-0)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS device timer 5-0 time-out register:
Bit(s)	Description	(Table P0356)
 15-6	reserved
 5-4	device timer time-out prescalar
	00 = 1 s
	01 = 10 s
	10 = 1 min.
	11 = 10 min.
 3-0	device timer time-out select
	0000 = disable
	0001-1001 = 1-9
	1010-1111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS device timer time-out source register 1:
Bit(s)	Description	(Table P0357)
 15	reserved
 14-12	keyboard activity device timer select
	000 = none
	001-110 = 0-5
	111 = reserved
 11-9	floppy disk activity device timer select (same values as bits 14-12)
 8-6	hard disk 2 activity device timer select (same values as bits 14-12)
 5-3	hard disk 1 activity device timer select (same values as bits 14-12)
 2-0	video activity device timer select (same values as bits 14-12)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS device timer time-out source register 2:
Bit(s)	Description	(Table P0358)
 15	reserved
 14-12	programmable range 1 activity device timer select
	000 = none
	001-110 = 0-5
	111 = reserved
 11-9	programmable range 0 activity device timer select (same values as
	  bits 14-12)
 8-6	parallel port activity device timer select (same values as bits 14-12)
 5-3	serial port 2 activity device timer select (same values as bits 14-12)
 2-0	serial port 1 activity device timer select (same values as bits 14-12)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS device timer time-out source register 3:
Bit(s)	Description	(Table P0359)
 15-12	reserved
 11-9	programmable range 5 activity device timer select
	000 = none
	001-110 = 0-5
	111 = reserved
 8-6	programmable range 4 activity device timer select (same values as
	  bits 11-9)
 5-3	programmable range 3 activity device timer select (same values as
	  bits 11-9)
 2-0	programmable range 2 activity device timer select (same values as
	  bits 11-9)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS device timer time-out source register 4:
Bit(s)	Description	(Table P0360)
 15-3	reserved
 2-0	EXTACT0 activity device timer select
	000 = none
	001-110 = 0-5
	111 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS LED indicator control register:
Bit(s)	Description	(Table P0361)
 15-13	reserved
 12-11	LED1 flash duration
	00 = 256 ms (cannot be set if flash rate is 2 or 4 Hz)
	01 = 128 ms (cannot be set if flash rate is 4 Hz)
	10 = 62.5 ms
	11 = 31.25 ms
 10-9	LED1 flash rate select
	00 = 0.5 Hz
	01 = 1 Hz
	10 = 2 Hz
	11 = 4 Hz
 8	LED1 flasher enable
 7-5	reserved
 4-3	LED0 flash duration (same values as bits 12-11)
 2-1	LED0 flash rate select (same values as bits 10-9)
 0	LED0 flasher enable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS leakage control register:
Bit(s)	Description	(Table P0362)
 15-2	reserved
 1	input leakage control during 5 V suspend enable
 0	output leakage control during 5 V suspend enable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS pin multiplexing control register:
Bit(s)	Description	(Table P0363)
 15	PC5 function
	0 = PC5
	1 = reserved
 14	PC4 function
	0 = PC4
	1 = LED1 output
 13	PC3 function
	0 = PC3
	1 = LED0 output
 12	reserved
 11-10	GPIO5 function
	00 = GPIO5
	01 = reserved
	10 = THERM input active-high
	11 = THERM input active-low
 9-8	GPIO4 function
	00 = GPIO4
	01 = reserved
	10 = (revision BB and later) SUSPA# input
	11 = reserved
 7-6	GPIO3 function
	00 = GPIO3
	01 = SUPPRESS_RESUME input
	10-11 = reserved
 5-4	GPIO2 function
	00 = GPIO2
	01 = DDMA_RETRY input
	10 = DPSLP_IRQPA input
	11 = reserved
 3-2	GPIO1 function
	00 = GPIO1
	01 = LED1 output
	10 = (revision BB and later) FLOAT_GNT# output
	11 = reserved
 1-0	GPIO0 function
	00 = GPIO0
	01 = LED0 output
	10 = (revision BB and later) FLOAT_REQ# input
	11 = reserved
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS debounce control register:
Bit(s)	Description	(Table P0364)
 15-5	reserved
 4	EXTACT0 debounce select
	0 = 0 s
	1 = 20 ms
 3	RING debounce select (same values as bit 4)
 2	WAKE1 debounce select (same values as bit 4)
 1	WAKE0 debounce select (same values as bit 4)
 0	SWTCH debounce select (same values as bit 4)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS edge detect control register:
Bit(s)	Description	(Table P0365)
 15-10	reserved
 9-8	EXTACT0 edge detect
	00 = reserved
	01 = falling
	10 = rising
	11 = rising and falling
 7-6	RING edge detect
	00 = reserved
	01 = falling
	10 = rising
	11 = reserved
 5-4	WAKE1 edge detect (same values as bits 9-8)
 3-2	WAKE0 edge detect (same values as bits 9-8)
 1-0	SWTCH edge detect (same values as bits 9-8)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS L2 cache configuration register:
Bit(s)	Description	(Table P0366)
 15-10	reserved
 9	TAG initialization enable
 8	NALE mode select
	0 = TAGCS#/NALE# pin is in TAGCS# mode
	1 = TAGCS#/NALE# pin is in NALE# mode
 7	pipelined burst SRAM enable (if bits 5-4 = 01)
 6	reserved
 5-4	L2 cache type
	00 = standard asynchronous
	01 = standard synchronous
	10-11 = reserved
 3-1	L2 cache size select
	000 = 128 KB
	001 = 256 KB
	010 = 512 KB
	011 = 1 MB
	100-111 = reserved
 0	L2 cache enable
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS L2 cache timing register:
Bit(s)	Description	(Table P0367)
 15-8	reserved
 7-6	L2 cache write follow-on
	00 = 1T
	01-11 = reserved
 5-4	L2 cache write leadoff
	00 = 2T
	01 = 3T
	10 = 4T
	11 = reserved
 3-2	L2 cache read follow-on (same values as bits 7-6)
 1-0	L2 cache read leadoff (same values as bits 5-4)
SeeAlso: #P0294

Bitfields for PicoPower Vesuvius V1-LS L2 cache miscellaneous register:
Bit(s)	Description	(Table P0368)
 15-10	reserved
 9-8	(revision BB and later) pipeline on memory read-miss cycle enable
	x0 = disable
	01 = enable (NA generated same time as first BRDY#)
	11 = enable (NA generated as soon as internal read request recognized)
 7	power management on CE# only for 50 MHz operation disable
 6	advanced synchronous power enhanced cache timing enable
 5-2	reserved
 1	invalidation of ROM address disable
 0	dead clock enable
SeeAlso: #P0294

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P00240029 - PORT 0024-0029 - HEADLAND HTK340 SHASTA 386/486 CHIPSET

PORT 0024-0029 - HEADLAND HTK340 SHASTA 386/486 CHIPSET

0024  Rw  data port
0028  ?W  index port to chipset registers (see #P0369,#P0370)

(Table P0369)
Values for Headland HT321 register index:
 00h R	chip/revision,read-only
	  bit7-4: reserved (=0)
	  bit3-0: chip revision, 0=A, 1=B, 3=D
 01h RW system clocking (default=00h)
	  bit7-4: reserved (=0)
	  bit3-0: ISA speed set
 02h RW system parameters (default=00h) (see #P0371)
 04h RW co-processor (default=00h)
	  bit7-3: reserved (=0)
	  bit2=1: soft-NPU reset blocked (386 only)
	  bit1=1: weitek installed
	  bit0=1: 387 installed
 06h RW DMA (default=00h) (see #P0372)
 07h RW EPROM (default=00h) (see #P0373)
 08h RW I/O and memory map holes (default=00h)
	  bit7-4: reserved (=0)
	  bit3	: 0/1 I/O map hole-A
	  bit2	: reserved (=0)
	  bit1	: 0/1 memory map hole-B
	  bit0	: reserved (=0)
 10h RW hole-A low address (default=00h)
 11h RW hole-A high address (default=00h)
 19h RW mem hole-B start address, lower (default=00h)
 1Ah RW mem hole-B start address, higher (default=00h)
	  bit7-6: reserved (=0)
	  bit5-0: address of mem hole-B start
 1Ch RW mem hole-B end address, lower (default=00h)
 1Dh RW mem hole-B end address, higher (default=00h)
	  bit7-6: reserved (=0)
	  bit5-0: address of mem hole-B end
SeeAlso: #P0370

(Table P0370)
Values for Headland HT342 register index:
 20h R	identifier port read
	  bit7-4: DRAM controller identifier (0010b)
	  bit3-0: revision number (0=A)
 21h R	feature port read    (default=00h)
 24h RW DRAM options port #1 (default=00h)
	  bit7	: 0/1 staggered refresh
	  bit6	: refresh type
	  bit5	: 0/1 DRAM paging
	  bit4-2: CAS interleave
	  bit1-0: banks
 25h	DRAM options port #2 (default=00h)
	  bit7-6: DRAM bank 1 type
	  bit5-4: DRAM bank 2 type
	  bit3-2: DRAM bank 1?? type
	  bit1-0: DRAM bank 0 type
 26h RW DRAM options port #3 (default=FFh) (see #P0374)
 27h RW DRAM options port #4 (default=FFh) (see #P0375)
 28h RW data transfer control port (default=00h)
	doubled indexed registers (28h-2Ah)
	  bit7	: initiate transfer
	  bit6	: read/write transfer
	  bit5-4: reserved
	  bit3-0: transfer/destination
 29h RW RAM address register (default=00h)
	doubled indexed registers (28h-2Ah)
	  bit7-5: reserved
	  bit4-0: RAM address registers contents
 2Ah RW data transfer port   (default=00h)
	doubled indexed registers (28h-2Ah)
	  bit7-6: reserved
	  bit5	: EMS translation
	  bit4	: reserved
	  bit3	: 0/1 cacheing
	  bit2	: 0/1 write
	  bit1	: 0/1 read
	  bit0	: 0/1 shadow
 2Bh RW other options	      (default=00h) (see #P0376)
 2Dh RW DRAM options port #5 (default=03h)
	  bit7-5: reserved
	  bit4	: 0/1 10æs RAS timeout
	  bit3-2: BUS speed
	  bit1-0: BUS recovery for DRAM cycles
		   00b=0: 4-1-1-1    10b=0.5
		   01b=1: 4-2-2-2    11b=1??
 82h	read transfer
 C2h	write transfer
SeeAlso: #P0369

Bitfields for Headland HT321 register 02h (system parameters):
Bit(s)	Description	(Table P0371)
 7-6	IO recovery time (rev. D+)
 5	parity override
 4-3	cycle-width
 2	0/1 PORT 0092h functionality
 1	IO decode
 0	0/1 posted backplane MEMWN cycles
SeeAlso: #P0369

Bitfields for Headland HT321 register 06h (DMA control):
Bit(s)	Description	(Table P0372)
 7	reserved (=0)
 6	1/0 IOCHRDY during master cycle (rev. C+)
 5	0/1 fast sample DMA
 4-3	DMA waitstate 00b=3 .. 11b=0
 2	0/1 DMA flow-through mode
 1	0/1 extended DMA page register
 0	DMA clock
SeeAlso: #P0369

Bitfields for Headland HT321 register 07h (EPROM control):
Bit(s)	Description	(Table P0373)
 7-6	reserved (=0)
 5	0/1 EADS CACHE invalidation for EPROM writes (rev. D+)
 4	0/1 ROMEN for EPROM writes (rev. C+)
 3	0/1 middle BIOS region of 64KB space below 16MB
 2	ROM-size (0=64KB, 1=128KB)
 1	V-BIOS-add (0=separate, 1=same device)
 0	ROM-access time (0=250ns, 1=125ns)
SeeAlso: #P0369

Bitfields for Headland HT342 register 26h (DRAM CAS control):
Bit(s)	Description	(Table P0374)
 7	CAS hold on RAS (CAS before RAS refresh)
 6	CAS precharge
 5	CAS burst delay
 4	CAS delay (writes)
 3	CAS delay (reads)
 2	CAS active time (writes)
 1-0	CAS active time (reads)
SeeAlso: #P0370,#P0375

Bitfields for Headland HT342 register 27h (DRAM RAS control):
Bit(s)	Description	(Table P0375)
 7	RAS delay
 6-5	RAS active (writes)
 4-2	RAS active (reads)
 1-0	RAS precharge
SeeAlso: #P0370,#P0374

Bitfields for Headland HT342 register 2Bh (other options):
Bit(s)	Description	(Table P0376)
 7	reserved
 6	0/1 middle BIOS
 5	0/1 data pipeline
 4	0/1 data pipeline
 3	IO-decode
 2	reserved
 1	16bit DMA bridge
 0	0/1 write buffering
SeeAlso: #P0370

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P00260027 - PORT 0026-0027 - INTEL 82347 POWER MANAGEMENT PERIPHERAL

PORT 0026-0027 - INTEL 82347 POWER MANAGEMENT PERIPHERAL
SeeAlso: PORT 0178h-0179h

0026  -W  index for data port (see #P0377)
0027  RW  power management data

(Table P0377)
Values for Intel 82437 Power Management Peripheral register index:
 C0h	suspend/wakeup status, system state
 C1h	power supply and activity status, general-purpose output/control
 C2h	control bits
 C3h	activity mask
 C4h	NMI mask
 C5h	I/O range for activity monitor
 C6h	power output control bits, ON state
 C7h	power output control bits, Doze state
 C8h	power output control bits, Sleep state
 C9h	power output control bits, Suspend state
 CAh	power control bits polarity control
 CBh	current output bits
 CCh	Doze timeout
 CDh	Sleep timeout
 CEh	Suspend timeout
 CFh	LCD display power timeout
 D0h	EL display power timeout

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P00260027 - PORT 0026-0027 - Chips&Technologies CS4021 - "SuperState V" ALTERNATE CONFIG

PORT 0026-0027 - Chips&Technologies CS4021 - "SuperState V" ALTERNATE CONFIG
Desc:	alternate copy of the configuration register access at PORT 0022h/0023h
	  which may be used by system software in "SuperState V" to configure
	  the chipset without disturbing accesses to PORT 0022h by user code
Notes:	SuperState V is an early version of system management mode
	these ports can only be accessed while the system is in SuperState V;
	  similarly, some configuration registers are read-only via PORT 0022h
	  and others can optionally be made read-only
SeeAlso: PORT 0022h"Chips&Technologies"
!!!chips\cs4021.pdf p.149

0026  -W  configuration register index
0027  RW  configuration register data

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P0028002A - PORT 0028-002A - 80486 "Deep Green" motherboard - ???

PORT 0028-002A - 80486 "Deep Green" motherboard - ???

0028  ?W  index for data port
002A  RW  ??? data port

Note:	in order to access to the registers available through PORT 002A,
	  an unlocking sequence must be written via PORT 0028:	write
	  A0h, 05h, index to PORT 0028, then read/write PORT 002A, then
	  write A5h to PORT 0028

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P002E002F - PORT 002E-002F - DELL ENHANCED PARALLEL PORT

PORT 002E-002F - DELL ENHANCED PARALLEL PORT
SeeAlso: PORT 015Ch,PORT 026Eh,PORT 0398h

002E  -W  index for data port (see #P0378)
002F  RW  EPP command data

(Table P0378)
Values for Dell Enhanced Parallel Port register index:
 00h	bit 0: ???
 02h	bit 7: port in bidirectional mode
 04h	bits 0 and 2: ECP/EPP mode control

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P002E002F - PORT 002E-002F - Intel "Nonolet" Motherboard - POWER MANAGEMENT

PORT 002E-002F - Intel "Nonolet" Motherboard - POWER MANAGEMENT

002E  ?W  index for data port
002F  ?W  data port

code sequence posted in fido7.nice.sources by Konstantin Mohorea:
     out 2Eh,0Ch
     out 2Fh,75h
     out 2Eh,11h
     out 2Fh,00h
     out 2Eh,0Dh
     out 2Fh,A0h

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P002E002F - PORT 002E-002F - NS PC87306 SuperI/O - CONFIGURATION REGISTERS

PORT 002E-002F - NS PC87306 SuperI/O - CONFIGURATION REGISTERS
InstallCheck: after a hardware reset, the first read of the index port returns
	  88h, and a second consecutive read always returns 00h (while
	  read-after-write always returns the written value)
Range:	PORT 002Eh, PORT 015Ch, PORT 026Eh, or PORT 0398h, depending on
	  external strapping
Note:	to set a register, the data port must be written twice in a row; the
	  value is latched on the second write

002E  RW  configuration register index
002F  RW  configuration register data

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P0038003F - PORT 0038-003F - PC radio by CoZet Info Systems

PORT 0038-003F - PC radio by CoZet Info Systems
Notes:	The I/O address range is dipswitch selectable from:
	   038-03F and 0B0-0BF
	   078-07F and 0F0-0FF
	   138-13F and 1B0-1BF
	   178-17F and 1F0-1FF
	   238-23F and 2B0-2BF
	   278-27F and 2F0-2FF
	   338-33F and 3B0-3BF
	   378-37F and 3F0-3FF
	All of these addresses show a readout of FF in initial state.
	Once started, all of the addresses show	 FB, whatever might happen.

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P0040005F - PORT 0040-005F - PIT - PROGRAMMABLE INTERVAL TIMER (8253, 8254)

PORT 0040-005F - PIT - PROGRAMMABLE INTERVAL TIMER (8253, 8254)
Notes:	XT & AT use ports 40h-43h; PS/2 uses ports 40h, 42h-44h, and 47h
	the counter chip is driven with a 1.193 MHz clock (1/4 of the
	original PC's 4.77 MHz CPU clock)
SeeAlso: PORT 0044h,PORT 0048h

0040  RW  PIT  counter 0, counter divisor	      (XT, AT, PS/2)
	Used to keep the system time; the default divisor of (1)0000h
	produces the 18.2Hz clock tick.
0041  RW  PIT  counter 1, RAM refresh counter	(XT, AT)
	don't set below 3 on PCs (default 12h), and don't mess with this
	counter at all unless you really know what you're doing....
0042  RW  PIT  counter 2, cassette & speaker	(XT, AT, PS/2)
	During normal operation mode (8253) 40h-42h set the counter values on
	write and get the current counter value on read. In 16bit modes two
	consequtive writes/reads must be issued, first with the low byte,
	followed by the high byte. In 8254 read back modes, all selected
	counters and status are latched and must be read out completely
	before normal operation is valid again.	 Each counter switches back
	to normal operation after read out.  In 'get status and counter'
	mode the first byte read is the status, followed by one or two
	counter values. (see #P0379)  Note that 16-bit reads performed
	without using the "latch" command will get the current high/low
	portion of the counter at the instant of the port read, so it is
	possible for the low part of the counter to wrap around before the
	high part gets read, resulting in a significant measurement error
0043  RW  PIT  mode port, control word register for counters 0-2 (see #P0380)
	Once a control word has been written (43h), it must be followed
	immediately by performing the corresponding action to the counter
	registers (40h-42h), else the system may hang!!

Bitfields for 8254 PIT counter status byte:
Bit(s)	Description	(Table P0379)
 7	PIN status of OUTx Pins (1=high, 0=low)
 6	counter start value loaded
	=0: yes, so counter latch is valid to be read
	=1: no, wait for counter latch to be set (may last a while)
5-0	counter mode, same as bit5-0 at 43h
SeeAlso: #P0380

Bitfields for 8253/8254 PIT mode control word:
Bit(s)	Description	(Table P0380)
 7-6	counter select
	00  counter 0 select
	01  counter 1 select	  (not PS/2)
	10  counter 2 select
	11  (8253) reserved
	    (8254) read back counter (see #P0379)
---if counter select---
 5-4	counter access
	00  counter latch command
		BUG:	Intel Neptune/Mercury/Aries Chipset 8237IB (SIO) needs
			  a short delay after issuing this command, else the
			  latched MSB may be outdated with respect to the LSB,
			  resulting in large measuring errors.
			Workaround: Check for this condition by comparing
			  results with last results and don't use erroneous
			  results.
	01  read/write counter bits 0-7 only
	10  read/write counter bits 8-15 only
	11  read/write counter bits 0-7 first, then 8-15
 3-1	counter mode
	000 mode 0 select - zero detection interrupt
	001 mode 1 select - programmable one shot
	x10 mode 2 select - rate generator
	x11 mode 3 select - square wave generator
		counts down twice by two at a time; latch status and check
		  value of OUT pin to determine which half-cycle is active
		divisor factor 3 not allowed!
	100 mode 4 select - software triggered strobe
	101 mode 5 select - hardware triggered strobe
 0	counting style
	0  binary counter 16 bits
	1  BCD counter (4 decades)
---if read back---
 5-4	what to read
	00 counter status, then value
	01 counter value
	10 counter status
	11 reserved
 3	select counter 2
 2	select counter 1
 1	select counter 0
 0	reserved (0)
Note:	after issuing a read back 'get status' command, any new read back
	  command is ignored until the status is read from all selected
	  counters.

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P00440047 - PORT 0044-0047 - Microchannel - PROGRAMMABLE INTERVAL TIMER 2

PORT 0044-0047 - Microchannel - PROGRAMMABLE INTERVAL TIMER 2
SeeAlso: PORT 0040h,PORT 0048h

0044  RW  PIT  counter 3 (PS/2)
		used as fail-safe timer. generates an NMI on time out.
		for user generated NMI see at 0462.
0047  -W  PIT  control word register counter 3 (PS/2, EISA)
	bit 7-6 = 00  counter 3 select
		= 01  reserved
		= 10  reserved
		= 11  reserved
	bit 5-4 = 00  counter latch command counter 3
		= 01  read/write counter bits 0-7 only
		= 1x  reserved
	bit 3-0 = 00

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P0048004B - PORT 0048-004B - EISA - PROGRAMMABLE INTERVAL TIMER 2

PORT 0048-004B - EISA - PROGRAMMABLE INTERVAL TIMER 2
Note:	this second timer is also supported by many Intel chipsets
SeeAlso: PORT 0040h,PORT 0044h

0048  RW  EISA PIT2 counter 3 (Watchdog Timer)
0049  ??  EISA 8254 timer 2, not used (counter 4)
004A  RW  EISA PIT2 counter 5 (CPU speed control)
004B  -W  EISA PIT2 control word

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P00500052 - PORT 0050-0052 - Olivetti M24 - 8530 SIO CHIP

PORT 0050-0052 - Olivetti M24 - 8530 SIO CHIP
SeeAlso: PORT 0065h"Olivetti"

0050  RW  8530 serial communications chip
Note:	At least MS-DOS 6 bypasses the initialization of serial devices if
	  it finds an Olivetti M24 machine with an 8630 SIO port present at
	  this address.
	An Olivetti-approved presence detection is to write 0Fh to port 50h
	  and check if bit 0 is still cleared when reading port 50h again.
SeeAlso: PORT 0066h, INT 14h/00h,INT 15h/C0h INTER 60 table 0515

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P0060006F - PORT 0060-006F - KEYBOARD CONTROLLER 804x (8041, 8042) (or PPI (8255) on PC,XT)

PORT 0060-006F - KEYBOARD CONTROLLER 804x (8041, 8042) (or PPI (8255) on PC,XT)
Note:	XT uses ports 60h-63h, AT uses ports 60h-64h

0060  RW  KB controller data port or keyboard input buffer (ISA, EISA)
		should only be read from after status port bit0 = 1
		should only be written to if status port bit1 = 0
0060  R-  KeyBoard or KB controller data output buffer (via PPI on XT)
		PC: input from port A of 8255, if bit7 in 61h set (see #P0396)
		get scancodes, special codes (in PC: with bit7 in 61h cleared)
		  (see #P0390)

0061  R-  KB controller port B control register (ISA, EISA)
		system control port for compatibility with 8255 (see #P0393)
0061  -W  KB controller port B (ISA, EISA)   (PS/2 port A is at 0092)
		system control port for compatibility with 8255 (see #P0392)
0061  -W  PPI Programmable Peripheral Interface 8255 (XT only)
		system control port (see #P0394)
0062  RW  PPI (XT only) data port C (see #P0395)
0063  RW  PPI (XT only) command mode register (see #P0397)

0064  R-  keyboard controller read status (see #P0398,#P0399,#P0400)
0064  -W  keyboard controller input buffer (ISA, EISA) (see #P0401)

0064  -W  (Amstrad/Schneider PC1512) set 'DIP switch S1' setting
	  stored in CMOS RAM that PPI should report for compatibility
0065  -W  (Amstrad/Schneider PC1512) set 'DIP switch S2' RAM size setting
	  stored in CMOS RAM, that PPI port C (PORT 0064h) should report for
	  compatibility

0065  R-  communications port (Olivetti M24)
0066  R?  configuration port (Olivetti M24 with model byte 0)
		bit 5 set if 8530 SIO present (see also PORT 0065h"Olivetti")

Bitfields for AT keyboard controller input port:
Bit(s)	Description	(Table P0381)
 7	keyboard enabled
 6	=0  CGA, else MDA
 5	=0  manufacturing jumper installed
 4	=0  system RAM 512K, else 640K
 3-0	reserved
SeeAlso: #P0382,#P0384

Bitfields for AT keyboard controller input port (Compaq):
Bit(s)	Description	(Table P0382)
 7	security lock is unlocked
 6	=0  Compaq dual-scan display, 1=non-Compaq display
 5	system board dip switch 5 is OFF
 4	=0  auto speed selected, 1=high speed selected
 3	=0  slow (4MHz), 1 = fast (8MHz)
 2	no math coprocessor installed
 1-0	reserved
SeeAlso: #P0383

Bitfields for AT keyboard controller output port:
Bit(s)	Description	(Table P0383)
 7	keyboard data output
 6	keyboard clock output
 5	input buffer NOT full
 4	output buffer NOT empty
 3	reserved (see note)
 2	reserved (see note)
 1	gate A20
 0	system reset
Note:	bits 2 and 3 are the turbo speed switch or password lock on
	  Award/AMI/Phoenix BIOSes.  These bits make use of nonstandard
	  keyboard controller BIOS functionality to manipulate
		pin 23 (8041 port 22) as turbo switch for AWARD
		pin 35 (8041 port 15) as turbo switch/pw lock for Phoenix
SeeAlso: #P0381,#P0384

Bitfields for HP Vectra keyboard controller output port:
Bit(s)	Description	(Table P0384)
 7-5	reserved
 4	output buffer full (OBF) interrupt
 3	HP SVC interrupt
 2	HP-HIL controller AutoPoll
 1	A20 gate
 0	system reset
SeeAlso: #P0383,#P0385

Bitfields for HP Vectra command byte:
Bit(s)	Description	(Table P0385)
 7	reserved (0)
 6	scancode conversion mode (1 = PC/XT, 0 = PC/AT)
 5	unused
 4	disable keyboard (unless bit 3 set)
 3	override keyboard disable
 2	System Flag (may be read from PORT 0060h)
 1	reserved
 0	OBF interrupt enable
SeeAlso: #P0384

(Table P0386)
Values for keyboard commands (data also goes to PORT 0060h):
Value	Count	Description
 EDh	double	set/reset mode indicators Caps Num Scrl
		bit 2 = CapsLk, bit 1 = NumLk, bit 0 = ScrlLk
		all other bits must be zero.
 EEh	sngl	diagnostic echo. returns EEh.
 EFh	sngl	NOP (No OPeration). reserved for future use
 EF+26h	double	[Cherry MF2 G80-1501HAD] read 256 bytes of chipcard data
		keyboard must be disabled before this and has to
		be enabled after finished.
 F0h	double	get/set scan code set
		00h get current set
		01h scancode set 1 (PCs and PS/2 mod 30, except Type 2 ctrlr)
		02h scancode set 2 (ATs, PS/2, default)
		03h scancode set 3
 F1h	???	select menu command
 F2h	sngl	read keyboard ID (read two ID bytes)
		AT keyboards returns FA (ACK)
		MF2 returns AB 41 (translation) or
			    AB 83 (pass through)
 F3h	double	set typematic rate/delay
		format of the second byte:
		bit7=0 : reserved
		bit6-5 : typemativ delay
			 00b=250ms     10b= 750ms
			 01b=500ms     11b=1000ms
		bit4-0 : typematic rate (see #P0391)
 F4h	sngl	enable keyboard
 F5h	sngl	disable keyboard. set default parameters (no keyboard scanning)
 F6h	sngl	set default parameters
 F7h	sngl	[MCA] set all keys to typematic (scancode set 3)
 F8h	sngl	[MCA] set all keys to make/release
 F9h	sngl	[MCA] set all keys to make only
 FAh	sngl	[MCA] set all keys to typematic/make/release
 FBh	sngl	[MCA] set al keys to typematic
 FCh	double	[MCA] set specific key to make/release
 FDh	double	[MCA] set specific key to make only
 FEh	sngl	resend last scancode
 FFh	sngl	perform internal power-on reset function
Note:	each command is acknowledged by FAh (ACK), if not mentioned otherwise.
	  See PORT 0060h-R for details.
SeeAlso: #P0387

(Table P0387)
Values for Mouse functions (for PS/2-like pointing devices):
Value	Count	Description
 E6h	sngl	set mouse scaling to 1:1
 E7h	sngl	set mouse scaling to 2:1
 E8h	double	set mouse resolution
		(00h=1/mm, 01h=2/mm, 02h=4/mm, 03h=8/mm)
 E9h	sngl	get mouse information
		read two status bytes:
		  byte 0: flags (see #P0388)
		  byte 1: resolution
 EAh	sngl	set mouse to stream mode (mouse sends data on any changes)
 EBh	sngl	get mouse data (from mouse to controller) (see #P0389)
		on reading, each data packet consists of 8 bytes:
 ECh	sngl	reset mouse wrap mode (to normal mode)
 EEh	sngl	set wrap mode
 F0h	sngl	set remote mode (instead of stream mode), mouse sends data
		  only on issueing command EBh.
 F2h	sngl	read mouse ID (read one, two?? ID bytes)
		00h=mouse
 F3h	double	set mouse sample rate in reports per second
		0Ah=10/s	   50h= 80/s
		14h=20/s	   64h=100/s
		28h=40/s	   C8h=200/s
		3Ch=60/s
 F4h	sngl	enable mouse (in stream mode)
 F5h	sngl	disable mouse (in steam mode), set default parameters
 F6h	sngl	reset to defaults: 100/s, scaling 1:1, stream-mode, 4/mm,
		  disabled
 FEh	sngl	resend last mouse data (8 bytes, see EBh)
 FFh	sngl	reset mouse
Notes:	 must issue command D4h to PORT 0064h first to access mouse functions
	 all commands except ECh and FFh are acknowledged by FAh (ACK) or
	   FEh (Resend); get mouse ID (F2h) returns mouse ID.
SeeAlso: #P0386

Bitfields for mouse status byte 0:
Bit(s)	Description	(Table P0388)
 7	unused
 6	remote rather than stream mode
 5	mouse enabled
 4	scaling set to 2:1
 3	unused
 2	left button pressed
 1	unused
 0	right button pressed
SeeAlso: #P0387,#P0389

Format of mouse data packet:
Offset	Size	Description	(Table P0389)
 00h	BYTE	status
		bit7	: y-data overrun
		bit6	: x-data overrun
		bit5	: y-data negative
		bit4	: x-data negative
		bit3-2=0: reserved
		bit1	: right button pressed
		bit0	: left button pressed
 01h	BYTE	reserved
 02h	BYTE	x-data
 03h	BYTE	reserved
 04h	BYTE	y-data
 05h	BYTE	reserved
 06h	BYTE	z-data (0)
 07h	BYTE	reserved
SeeAlso: #P0387,#P0388

(Table P0390)
Values for keyboard special codes:
 00h	(MF2 in codeset2&3 or AT keyboards) keydetection/overrun error
 00h	(mouse) ID
 AAh	BAT completion code (sent after errorfree Basic Assurance Test)
 ABh	first byte of general MF2 keyboard ID
 EEh	Echo command return
 F0h	keyboard break code
 FAh	Acknowledge (all general commands except Resend and Echo)
 FAh	(mouse) Acknowledge (all commands except commands ECh,F2h,FFh)
 FCh	(MF2) BAT Failure Code (error in second half of the power on self test)
 FDh	(AT-keyboard) BAT Failure Code (error in the second half of the
	  power-on self test)
 FEh	Resend: CPU to controller should resend last keyboard-command
 FEh	(mouse) CPU to controller should resend last mouse-command
 FFh	(MF2 in codeset1) keydetection/overrun error
Note:	keyboard stops scanning and waits for next command after returning
	  code FCh or FDh
SeeAlso: PORT 0060h-R

(Table P0391)
Values for keyboard typematic rate:
 00000b=30.0   10000b=7.5
 00001b=26.7   10001b=6.7
 00010b=24.0   10010b=6.0
 00011b=21.8   10011b=5.5
 00100b=20.0   10100b=5.0
 00101b=18.5   10101b=4.6
 00110b=17.1   10110b=4.3
 00111b=16.0   10111b=4.0
 01000b=15.0   11000b=3.7
 01001b=13.3   11001b=3.3
 01010b=12.0   11010b=3.0
 01011b=10.9   11011b=2.7
 01100b=10.0   11100b=2.5
 01101b= 9.2   11101b=2.3
 01110b= 8.5   11110b=2.1
 01111b= 8.0   11111b=2.0
SeeAlso: #P0386

Bitfields for KB controller port B (system control port) [output]:
Bit(s)	Description	(Table P0392)
 7	pulse to 1 for IRQ1 reset (PC,XT)
 6-4	reserved
 3	I/O channel parity check disable
 2	RAM parity check disable
 1	speaker data enable
 0	timer 2 gate to speaker enable
SeeAlso: PORT 0061h-W,#P0393

Bitfields for KB ctrller port B control register (system control port) [input]:
Bit(s)	Description	(Table P0393)
 7	RAM parity error occurred
 6	I/O channel parity error occurred
 5	mirrors timer 2 output condition
 4	toggles with each refresh request
 3	NMI I/O channel check status
 2	NMI parity check status
 1	speaker data status
 0	timer 2 clock gate to speaker status
Note:	also supported by OPTi 82C392
SeeAlso: PORT 0061h-R,#P0392

Bitfields for Progr. Peripheral Interface (8255) system control port [output]:
Bit(s)	Description	(Table P0394)
 7	clear keyboard (only pulse, normally kept at 0)
 6	=0  hold keyboard clock low
 5	NMI I/O parity check disable
 4	NMI RAM parity check disable
 3	=0 read low nybble of switches S2
	=1 read high nybble of switches S2
 2	reserved, often used as turbo switch
	original PC: cassette motor off
 1	speaker data enable
 0	timer 2 gate to speaker enable
Note:	bits 2 and 3 are sometimes used as turbo switch
SeeAlso: PORT 0061h-W,#P00051,#P0395,#P0396,#P0397

Bitfields for PPI (XT only) data port C:
Bit(s)	Description	(Table P0395)
 7	RAM parity error occurred
 6	I/O channel parity error occurred
 5	timer 2 channel out
 4	reserved
	original PC: cassette data input
---
 3	system board RAM size type 1
 2	system board RAM size type 2
 1	coprocessor installed
 0	loop in POST
---
 3-0	DIL switch S2 high/low nybble (depending on PORT 0061h bit 3)
SeeAlso: PORT 0062h-RW,#P0394,#P0396,#P0397

Bitfields for PPI (PC,XT only) equipment switches [input]:
Bit(s)	Description	(Table P0396)
 7-6	number of disk drives
	00  1 diskette drive
	01  2 diskette drives
	10  3 diskette drives
	11  4 diskette drives
 5-4	initial video
	00  reserved (video adapter has on-board BIOS)
	01  40*25 color (mono mode)
	10  80*25 color (mono mode)
	11  MDA 80*25
 3-2	memory size (using 256K chips)
	00  256K
	01  512K
	10  576K
	11  640K
 3-2	memory size (using 64K chips)
	00  64K
	01  128K
	10  192K
	11  256K
 3-2	memory size (original PC)
	00  16K
	01  32K
	10  48K
	11  64K
 1-0	reserved
 1	NPU (math coprocessor) present
 0	boot from floppy
SeeAlso: #P0395,#P0397,PORT 0060h-R

Bitfields for PPI (8255) command mode register:
Bit(s)	Description	(Table P0397)
 7	activation function (0 = bit set/reset, 1 = mode set function)
 6,5	port A mode: 00 = mode0, 01 = mode1, 1x = mode2
 4	port A direction: 0 = output, 1 = input
 3	port C bits 7-4 direction: 0 = output, 1 = input
 2	port B mode: 0 = mode0, 1 = mode1
 1	port B direction: 0 = output, 1 = input
 0	port C bits 3-0 direction: 0 = output, 1 = input
Note:	Attention: Never write anything other than 99h to this port
	  (better: never write anything to this port, only during BIOS
	  init), as other values may connect multiple output drivers
	  and will cause hardware damage in PC/XTs!  By setting command
	  word to 99h, PPI will be set in input/output modes as it is
	  necessary to support the commonly known IO-ports 60, 61, 62
	  as desired.
SeeAlso: #P0394,#P0395,#P0396

Bitfields for keyboard controller read status (ISA, EISA):
Bit(s)	Description	(Table P0398)
 7	parity error on transmission from keyboard
 6	receive timeout
 5	transmit timeout
 4	keyboard interface inhibited by keyboard lock
	or by password server mode (IBM PS/2-286 [model bytes FCh/09h],
	  "Tortuga" [model F8h/19h]) (see #00515 at INT 15/AH=C0h)
 3	=1 data written to input register is command (PORT 0064h)
	=0 data written to input register is data (PORT 0060h)
 2	system flag status: 0=power up or reset	 1=selftest OK
 1	input buffer full (input 60/64 has data for 8042)
	no write access allowed until bit clears
 0	output buffer full (output 60 has data for system)
	bit is cleared after read access
SeeAlso: PORT 0064h-R,#P0399,#P0400,#P0401

Bitfields for keyboard controller read status (MCA):
Bit(s)	Description	(Table P0399)
 7	parity error on transmission from keyboard
 6	general timeout
 5	mouse output buffer full
 4	keyboard interface inhibited by keyboard lock
 3	=1 data written to input register is command (PORT 0064h)
	=0 data written to input register is data (PORT 0060h)
 2	system flag status: 0=power up or reset	 1=selftest OK
 1	input buffer full (60/64 has data for 804x)
	no write access allowed until bit clears
 0	output buffer full (output 60 has data for system)
	bit is cleared after read access
SeeAlso: #P0398,#P0400,#P0401

Bitfields for keyboard controller read status (Compaq):
Bit(s)	Description	(Table P0400)
 7	parity error detected (11-bit format only). If an
	  error is detected, a Resend command is sent to the
	  keyboard once only, as an attempt to recover.
 6	receive timeout. transmission didn't finish in 2mS.
 5	transmission timeout error
	bit 5,6,7  cause
		1 0 0  No clock
		1 1 0  Clock OK, no response
		1 0 1  Clock OK, parity error
 4	=0 security lock engaged
 3	=1 data in OUTPUT register is command
	=0 data in OUTPUT register is data
 2	system flag status: 0=power up or reset	 1=soft reset
 1	input buffer full (60/64 has data for 804x)
	no write access allowed until bit clears
 0	output buffer full (PORT 0060h has data for system)
	bit is cleared after read access
SeeAlso: #P0398,#P0399,#P0401

(Table P0401)
Values for keyboard controller commands (data goes to PORT 0060h):
Value		Description
 20h	read	read byte zero of internal RAM, this is the last KB command
		  sent to the 8041/8042
	Compaq	put current command byte on PORT 0060h (see #P0403,#P0404)
 21-3F	read	reads the byte specified in the lower 5 bits of the command
		  in the 804x's internal RAM (see #P0407)
 60-7F	double	writes the data byte to the address specified in the 5 lower
		  bits of the command
 60h	Compaq	Load new command (60 to [64], command to [60]) (see #P0404)
		(also general AT-class machines)
 A0h	AMI	get ASCIZ copyright message on PORT 0060h
 A1h	AMI	get controller version byte on PORT 0060h
 A1h	Compaq	unknown speedfunction ??
 A1h	C&T	CHIPS extensions (see #P0402)
 A2h	Compaq	unknown speedfunction ??
 A2h	AMI	set keyboard controller pins 22 and 23 low
 A2h	C&T	turn on turbo LED
 A3h	Compaq	Enable system speed control
 A3h	AMI	set keyboard controller pins 22 and 23 high
 A3h	C&T	turn off turbo LED
 A4h	MCA	check if password installed
		returns PORT 0060h code F1h if no password, FAh if installed
 A4h	Compaq	Toggle speed
 A4h	AMI	set internal system speed flag to low
 A5h	MCA	load password
		write successive scan codes to PORT 0060h, terminate with 00h
 A5h	AMI	set internal system speed flag to high
 A5h	Compaq	Special read. the 8042 places the real values of port 2
		  except for bits 4 and 5 wich are given a new definition in
		  the output buffer. No output buffer full is generated.
			if bit 5 = 0, a 9-bit keyboard is in use
			if bit 5 = 1, an 11-bit keyboard is in use
			if bit 4 = 0, output-buff-full interrupt disabled
			if bit 4 = 1, output-buffer-full interrupt enabled
 A6h	MCA	check password
 A6h	AMI	get internal system speed flag on PORT 0060h
 A6h	Compaq	unknown speedfunction ??
 A7h	MCA	disable mouse port
 A7h	AMI	set internal flag indicating bad write cache
 A8h	MCA	enable mouse port
 A8h	AMI	set internal flag indicating good write cache
 A9h	MCA	test mouse port, return test result on PORT 0060h (see #P0406)
 A9h	AMI	get internal flag indicating cache OK to PORT 0060h
 AAh	sngl	initiate self-test. will return 55h to data port if self-test
		  successful, FCh if failed
 AAh	Compaq	initializes ports 1 and 2, disables the keyboard and clears
		  the buffer pointers. It then places 55h in the output buffer.
 ABh	sngl	initiate interface test, return result value on PORT 0060h
		  (see #P0406)
 ACh	read	diagnostic dump. the contents of the 804x RAM, output port,
		  input port, status word are sent to PORT 0060h in scan-code
		  format; Chips&Technologies 8042's append "CHIPS Vxxx" where
		  "xxx" is the controller version number
 ADh	sngl	disable keyboard (sets bit 4 of commmand byte)
 ADh	Vectra	HP Vectra diagnostic dump
 AEh	sngl	enable keyboard	 (resets bit 4 of commmand byte)
 AFh	AWARD	Enhanced Command: read keyboard version
 AFh	AMI	set extended controller RAM
		write address to PORT 0060h, wait for controller ready, then
		  write value to PORT 0060h
 B1h	AMI	set keyboard controller P11 line low
 B2h	AMI	set keyboard controller P12 line low
 B3h	AMI	set keyboard controller P13 line low
 B4h	AMI	set keyboard controller P22 line low
 B5h	AMI	set keyboard controller P23 line low
 B8h	AMI	set keyboard controller P10 line high
 B9h	AMI	set keyboard controller P11 line high
 BAh	AMI	set keyboard controller P12 line high
 BBh	AMI	set keyboard controller P13 line high
 BCh	AMI	set keyboard controller P22 line high
 BDh	AMI	set keyboard controller P23 line high
 C0h	read	read input port and place on PORT 0060h
		bit 7	keyboard NOT locked
		bit 6	=0 first video is CGA
			=1 first video is MDA
		bit 5	=0 factory testmode
			=1 normal
		bit 4	=0 256KB RAM, 1=512KB
		bit 5,3-0 are used in Intel chipset 386sx machines with
			AMI/Phoenix BIOSes for BIOS specific hardware settings
		bit 2	(MCA) no keyboard power
		bit 1	(MCA) current mouse serial data input state
		bit 0	(MCA) current keyboard serial input state
 C0h	Compaq	places status of input port in output buffer.  Use this
		  command only when the output buffer is empty
 C1h	MCA	Enhanced Command: poll input port Low nibble, continuously
		  place in PORT 0064h bits 7-4 until next command
 C2h	MCA	Enhanced Command: poll input port High nibble, continuously
		  place in PORT 0064h bits 7-4 until next command
 C8h	AMI	unblock keyboard controller lines P22 and P23
 C9h	AMI	block keyboard controller lines P22 and P23
 CAh	AMI	read keyboard mode, return in 0060 bit 0
		  (bit clear if ISA mode, set if PS/2 mode)
 CBh	AMI	set keyboard mode (write back mode byte returned by CAh,
		  modifying only bit 0)
 CCh	AMI	??? (used by AMI BIOS v1.00.12.AX1T APM code)
 D0h	read	read output port and place on PORT 0060h (see #P0405)
 D0h	Compaq	places byte in output port in output buffer. Use this command
		  only when the output buffer is empty
 D1h	double	write output port.  The next byte written to PORT 0060h will
		  be written to the 804x output port; the original IBM AT and
		  many compatibles such as the OPTi 82C392 use bit 1 of the
		  output port to control the A20 gate.
		Important: bit 0 (system reset) should always be set here, as
			  the system may hang constantly; use pulse output port
			  (FEh) instead.
 D1h	Compaq	the system speed bits are not set by this command use
		  commands A1-A6 (!) for speed functions.
 D2h	MCA	Enhanced Command: write keyboard output buffer
 D3h	MCA	Enhanced Command: write pointing device out.buf.
 D4h	MCA	write to mouse/pointing device instead of to keyboard; this
		  controller command must precede every PORT 0060h command
		  directed to the mouse, otherwise it will be sent to the
		  keyboard
 D4h	AWARD	Enhanced Command: write to auxiliary device
 DDh	sngl	disable address line A20 (HP Vectra only???)
		default in Real Mode
 DFh	sngl	enable address line A20 (HP Vectra only???)
 E0h	read	read test inputs, and place in PORT 0060h
		bit0 = kbd clock, bit1 = kbd data
 Exxx	AWARD	Enhanced Command: active output port
 E5h	GoldStar set turbo LED color to yellow (turbo off)
 E7h	GoldStar set turbo LED color to yellow (turbo off)
 E8h	GoldStar set turbo LED color to green (turbo on)
 EAh	GoldStar set turbo LED color to green (turbo on)
 EDh	double	this is a two part command to control the state of the
		  NumLock, CpasLock and ScrollLock LEDs
		The second byte contains the state to set LEDs.
		    bit 7-3	reserved. should be set to 0.
		    bit 2 = 0	Caps Lock LED off
		    bit 1 = 0	Num Lock LED off
		    bit 0 = 0	Scroll Lock LED off
 F0-FF	sngl	pulse output port low for 6 microseconds.
		bits 0-3 contain the mask for the bits to be pulsed.  A bit is
		  pulsed if its mask bit is zero
		bit0=system reset. Don't set to zero. Pulse only!
Note:	 keyboard controllers are widely different from each other.  You
	   cannot generally exchange them between different machines.
	 (Award) Derived from Award's Enhanced KB controller advertising sheet.
	 (Compaq) Derived from the Compaq Deskpro 386 Tech. Ref. Guide.

(Table P0402)
Values for Chips&Technologies extension commands:
 00h	return ID - returns A6h for a C&T controller, part # N93N8042/A
 02h	write input port
	next data byte to PORT 0060h is written to the controller's input port
	Warning: the system must be designed to support output devices
		  connected to the input port to avoid potential damage
 04h	select turbo switch input
	next byte selects input:
	    bit 7: switch polarity
		(=0 input low = high speed, =1 input low = low speed)
	    bits 6-0: one bit set selects corresponding bit in Port1 as turbo
 05h	select turbo LED output
	next byte selects output:
	    bit 7: LED polarity	(=0 output low=LED on, =1 output low=LED off)
	    bit 6: LED port (=0 Port1, =1 Port2)
	    bits 5-0: one bit set selects corresponding bit in Port1/Port2 as
		LED output
Note:	these commands and any arguments are sent to PORT 0060h after writing
	  command A1h to PORT 0064h
SeeAlso: #P0401

Bitfields for Compaq keyboard command byte:
Bit(s)	Description	(Table P0403)
 7	reserved
 6	=1 convert KB codes to 8086 scan codes
 5	=0 use 11-bit codes, 1=use 8086 codes
 4	=0 enable keyboard, 1=disable keyboard
 3	ignore security lock state
 2	this bit goes into bit2 status reg.
 1	reserved (0)
 0	generate interrupt (IRQ1) when output buffer full
SeeAlso: #P0404

Bitfields for keyboard command byte (alternate description):
Bit(s)	Description	(Table P0404)
 7	reserved (0)
 6	IBM PC compatibility mode
 5	IBM PC mode
	no parity, no stop bits, no translation
	(PS/2) force mouse clock low
 4	disable keyboard (clock)
 3	(AT) inhibit override -- ignore keyboard lock switch
	(PS/2) reserved
 2	system flag
 1	(AT) reserved (0)
	(PS/2) enable mouse output buffer full interrupt (IRQ12)
 0	enable output buffer full interrupt (IRQ1)
SeeAlso: #P0403,#P0405

Bitfields for keyboard controller output port:
Bit(s)	Description	(Table P0405)
 7	keyboard data (output)
 6	keyboard clock (output)
 5	(AT) =0 input buffer empty
	(MCA) outptu buffer full with mouse byte (connected to IRQ12)
 4	output buffer full with keyboard byte (connected to IRQ1)
 3	(MCA) mouse data (output)
 2	(MCA) mouse clock (output)
	used by Intel 386sx Chipset with AMI/Phoenix BIOSes for BIOS-specific
	  configuration of turbo switch
 1	gate address A20
 0	system reset
Note:	bit 0 (system reset) should always be set when writing the output
	  port, as the system may hang constantly; use pulse output port
	  (command FEh) instead.
SeeAlso: #P0404

(Table P0406)
Values for keyboard/mouse test result on PORT 0060h:
 00h	no error
 01h	keyboard clock line stuck low
 02h	keyboard clock line stuck high
 03h	keyboard data line is stuck low
 04h	keyboard data line stuck high
 05h	(Compaq only) diagnostic feature
SeeAlso: #P0401

(Table P0407)
Values for keyboard controller RAM location:
 00h	command byte (see #P0403,#P0404)
---MCA systems---
 13h	security on
	nonzero if password enabled
 14h	security off
	nonzero if password matched
 16h	password discard scancode 1
 17h	password discard scancode 2
Note:	make codes matching either discard scancode are ignored during password
	  entry

Top

P0065 - PORT 0065 - AT&T 6300+ - HIGH/LOW CHIP SELECT

PORT 0065 - AT&T 6300+ - HIGH/LOW CHIP SELECT

Top

P0065 - PORT 0065 - ???

PORT 0065 - ???

0065  RW  ???
		bit 2: A20 gate control (set = A20 enabled, clear = disabled)

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P00650066 - PORT 0065-0066 - Olivetti M24

PORT 0065-0066 - Olivetti M24
SeeAlso: PORT 0050h"Olivetti"

0065  R-  communications port
0066  R?  configuration port
		Olivetti M24 at least with model byte 0 (see MEM F000h:FFFEh)
		bit 5 set if 8530 SIO installed at PORT 0050h
Note:	At least MS-DOS 6 bypasses the initialization of serial devices if
	  it finds an Olivetti M24 machine with an 8530 SIO present at ports
	  50h-52h.
!SeeAlso: PORT 0050h"Olivetti",INT 14/AH=00h,#00515 at INT 15/AH=C0h

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P00660067 - PORT 0066-0067 - AT&T 6300+ - SYSTEM CONFIGURATION SWITCHES

PORT 0066-0067 - AT&T 6300+ - SYSTEM CONFIGURATION SWITCHES

Top

P0066 - PORT 0066 - IBM 4717 Magnetic Stripe Reader - ???

PORT 0066 - IBM 4717 Magnetic Stripe Reader - ???
SeeAlso: PORT 0069h"Magnetic Stripe"

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P0068 - PORT 0068 - C&T CHIPSETS - TURBO MODE CONTROL

PORT 0068 - C&T CHIPSETS - TURBO MODE CONTROL

Note:	  on Micronics 386-25/386-33/486-25 motherboards, setting this port to
	    00h enables full speed; setting it to C0h slows the system down by
	    a factor corresponding to the value programmed into the EISA
	    interval timer 2 at ports 004Ah and 004Bh

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P0068006F - PORT 0068-006F - HP Vectra Human Interface Link

PORT 0068-006F - HP Vectra Human Interface Link
SeeAlso: PORT 0060h"KEYBOARD"

0068  -W  (HP-Vectra) control buffer (HP commands) (see #P0408)
0069  R-  (HP-Vectra) SVC (keyboard request SerViCe port)
006A  -W  (HP-Vectra) Acknowledge (clear processing, done)
006C-006F	HP-HIL	(Human Interface Link = async. serial inputs 0-7)

(Table P0408)
Values for HP Vectra control buffer command code:
 00h-54h insert standard key make code into 8041 scancode buf
 55h-77h insert HP key make code into 8041 scancode buffer
 7Ah	pass through next data byte
 7Bh	set RAM Switch to 0
 7Ch	set RAM Switch to 1 (default)
 7Dh	set CRT Switch to 0
 7Eh	set CRT Switch to 1 (default)
 7Fh	reserved
 80h-D4h insert standard key break code into scancode buffer
 D5h-F7h insert HP key break code into scancode buffer
 F8h	enable AutoPoll
 F9h	disable AutoPoll
 FAh-FEh reserved
 FFh	keyboard overrun

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P0069 - PORT 0069 - IBM 4717 Magnetic Stripe Reader - ???

PORT 0069 - IBM 4717 Magnetic Stripe Reader - ???
SeeAlso: PORT 0066h"Magnetic Stripe"

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P006B006F - PORT 006B-006F - SSGA CONTROL REGISTERS

PORT 006B-006F - SSGA CONTROL REGISTERS

006B  ??  RAM enable/remap
006C  ??  undocumented
006D  ??  undocumented
006E  ??  undocumented
006F  ??  undocumented

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P0070007F - PORT 0070-007F - CMOS RAM/RTC (REAL TIME CLOCK)

PORT 0070-007F - CMOS RAM/RTC (REAL TIME CLOCK)
Note:	the real-time clock may be either a discrete MC146814, MC146818, or
	  an emulation thereof built into the motherboard chipset
SeeAlso: PORT 00A0h"XT"

0070  -W  CMOS RAM index register port (ISA, EISA)
		 bit 7	= 1  NMI disabled from reaching CPU
			= 0  NMI enabled
		 bit 6-0     CMOS RAM index
			(64 bytes in early systems, now usually 128 bytes)
	Note:	any write to PORT 0070h should be followed by an action to
		  PORT 0071h or the RTC wil be left in an unknown state.
0071  RW  CMOS RAM data port (ISA, EISA) (see #P0409)

(Table P0409)
Values for Real-Time Clock register number (see also CMOS.LST):
 00h-0Dh clock registers
 0Eh	diagnostics status byte
 0Fh	shutdown status byte
 10h	diskette drive type for A: and B:
 11h	reserved / IBM fixed disk / setup options
 12h	fixed disk drive type for drive 0 and drive 1
 13h	reserved / AMI Extended CMOS setup (AMI Hi-Flex BIOS)
 14h	equipment byte
 15h	LSB of system base memory in Kb
 16h	MSB of system base memory in Kb
 17h	LSB of total extended memory in Kb
 18h	MSB of total extended memory in Kb
 19h	drive C extension byte
 1Ah	drive D extension byte
 1Bh-2Dh reserved
 20h-27h commonly used for first user-configurable drive type
 2Eh	CMOS MSB checksum over 10-2D
 2Fh	CMOS LSB checksum over 10-2D
 30h	LSB of extended memory found above 1Mb at POST
 31h	MSB of extended memory found above 1Mb at POST
 32h	date century in BCD
 33h	information flags
 34h-3Fh	reserved
 35h-3Ch commonly used for second user-configurable drive type
 3Dh-3Eh word to 82335 MCR memory config register at [22] (Phoenix)
 42h-4Ch AMI 1990 Hyundai super-NB368S notebook
	???
 54h-57h AMI 1990 Hyundai super-NB368S notebook
	???
 5Ch-5Dh AMI 1990 Hyundai super-NB368S notebook
	???
 60h-61h AMI 1990 Hyundai super-NB368S notebook
	???

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P0072 - PORT 0072 - Chips&Technologies 82C100 - NMI CONTROL

PORT 0072 - Chips&Technologies 82C100 - NMI CONTROL

!!!chips\82c100.pdf p.41

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P00720075 - PORT 0072-0075 - AMD-645 Peripheral Bus Controller - ACCESS TO EXTENDED CMOS

PORT 0072-0075 - AMD-645 Peripheral Bus Controller - ACCESS TO EXTENDED CMOS
SeeAlso: PORT 0070h

0072  RW  CMOS memory address, region 2 (256 bytes)
0073  RW  CMOS memory data, region 2
0074  RW  CMOS memory address, region 3 (256 bytes)
0075  RW  CMOS memory data, region 3
Note:	on the AMD-645, ports 0072h and 0073h allow access to a full 256 bytes
	  of RAM, including the standard 128 bytes available through ports
	  0070h and 0071h

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P0073 - PORT 0073 - Intel 82378IB ("Saturn"/"Neptune" chipsets) - MBOARD CONFIGURATION

PORT 0073 - Intel 82378IB ("Saturn"/"Neptune" chipsets) - MBOARD CONFIGURATION
SeeAlso: PORT 0075h

0073  RW  ???
	bit 7: ???
	bit 6: disable ROM shadowing
	bit 5: ??? (related to IDE controller)
	bit 4: ???
	bit 3: ???

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P00740076 - PORT 0074-0076 - SECONDARY CMOS (Compaq), NVRAM (IBM) ACCESS

PORT 0074-0076 - SECONDARY CMOS (Compaq), NVRAM (IBM) ACCESS
Note:	NVRAM may be 2K, 8K, or 16K
SeeAlso: PORT 0070h-007Fh,CMOS.LST

0074  -W  secondary CMOS RAM (IBM NVRAM) index, low byte
0075  -W  secondary CMOS RAM (IBM NVRAM) index, high (in bits 2-0)
0076  RW  secondary CMOS RAM (IBM NVRAM) data byte

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P0075 - PORT 0075 - Intel 82378IB ("Saturn"/"Neptune" chipsets) - MBOARD CONFIGURATION

PORT 0075 - Intel 82378IB ("Saturn"/"Neptune" chipsets) - MBOARD CONFIGURATION
SeeAlso: PORT 0073h,PORT 0078h"82378IB"

0075  R-  ???
	  bits 3-2: external bus speed
	       00  50 MHz
	       01  66 MHz
	       10  60 MHz
	       11  40 MHz

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P0078 - PORT 0078 - HP-Vectra - HARD RESET: NMI ENABLE/DISABLE

PORT 0078 - HP-Vectra - HARD RESET: NMI ENABLE/DISABLE

0078  ?W  NMI enable/disable
		bit 7 = 0  disable & clear hard reset from HP-HIL controller
		      = 1  enable hard reset from HP-HIL controller chip
		bit 6-0	   reserved

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P0078 - PORT 0078 - Intel 82378IB ("Saturn"/"Neptune" chipsets) - BIOS COUNT-DOWN TIMER

PORT 0078 - Intel 82378IB ("Saturn"/"Neptune" chipsets) - BIOS COUNT-DOWN TIMER
Notes:	the BIOS uses this port for certain fine timings; presumably it is
	  independent of processor speed (it appears to decrement at 1 MHz)
	the address at which this port appears may be set via the 82378's
	  PCI configuration space word at offset 0080h (see #01064), or the
	  timer may be disabled entirely
SeeAlso: PORT 0075h

0078w -W  set count-down timer
0078w R-  get current count (timer stops when it reaches 0000h)

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P0078007F - PORT 0078-007F - PC radio by CoZet Info Systems

PORT 0078-007F - PC radio by CoZet Info Systems
Range:	The I/O address range is dipswitch selectable from:
	   038-03F and 0B0-0BF
	   078-07F and 0F0-0FF
	   138-13F and 1B0-1BF
	   178-17F and 1F0-1FF
	   238-23F and 2B0-2BF
	   278-27F and 2F0-2FF
	   338-33F and 3B0-3BF
	   378-37F and 3F0-3FF
Note:	All of these addresses show a readout of FFh in initial state.
	Once started, all of the addresses show FBh, whatever might happen.

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P007C007D - PORT 007C-007D - HP-Vectra - PIC 3 - PROGRAMMABLE INTERRUPT CONTROLLER (8259)

PORT 007C-007D - HP-Vectra - PIC 3 - PROGRAMMABLE INTERRUPT CONTROLLER (8259)
Notes:	cascaded to first controller.
	used for keyboard and input device interface.
SeeAlso: PORT 0020h-0021h,INT 68"Vectra",INT 6E"Vectra"

007C  RW  HP-Vectra  PIC 3  see at 0020	 PIC 1
007D  RW  HP-Vectra  PIC 3  see at 0021	 PIC 1

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P007E - PORT 007E - Chips&Technologies 82C100/110 - NMI STATUS

PORT 007E - Chips&Technologies 82C100/110 - NMI STATUS
SeeAlso: PORT 0072h"82C100",PORT 007Fh"82C100"
!!!chips\82c100.pdf p.42
!!!chips\82c110.pdf p.39

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P007F - PORT 007F - Chips&Technologies 82C100/110 - POWER CONTROL AND RESET

PORT 007F - Chips&Technologies 82C100/110 - POWER CONTROL AND RESET
SeeAlso: PORT 0072h"82C100",PORT 007Eh"82C100"

Top

P0080 - PORT 0080 - MANUFACTURING DIAGNOSTICS PORT

PORT 0080 - MANUFACTURING DIAGNOSTICS PORT
Note:	sometimes used for a POST hex display

0080  -W  Manufacturing Diagnostics port
0080  R-  ???

(Table P0410)
Values for AMI BIOS diagnostics codes:
 00h	system boot completed, control passed to INT 19 bootstrap loader
 01h	register test
 02h	video initialization; NMIs disabled
 03h	power-on delay complete
 04h	pre-keyboard-test initializations complete
 05h	soft-reset/power-on setting determined
 06h	ROM enabled
 07h	ROM BIOS checksum test passed
 08h	keyboard BAT command issued
 09h	keyboard controller BAT result verified
 0Ah	keyboard controller command code issued
 0Bh	keyboard controller command byte written
 0Ch	keyboard controller pins 23/24 blocked and unblocked
 0Dh	keyboard controller NOP processing in progress
 0Eh	CMOS RAM shutdown register read/write test passed
 0Fh	CMOS RAM checksum calculation complete
 10h	CMOS RAM initialization complete
 11h	CMOS RAM status register initialized
 12h	DMA controllers 1/2 and interrupt controllers 1/2 disabled
 13h	video display disabled, port B initialized
 14h	chipset initialization, auto memory detection
 15h	8254 channel 2 test half complete
 16h	8254 channel 2 test completed
 17h	8254 channel 1 test completed
 18h	8254 channel 0 test completed
 19h	memory refresh started
 1Ah	memory refresh line is toggling
 1Bh	memory refresh test completed
 20h	base 64K memory test started
 21h	address line test passed
 22h	parity toggle complete
 23h	base 64K sequential read/write test passed
 24h	pre-interrupt-vector-initialization configuration complete
 25h	interrupt vectors initialized
 26h	8042 input port read
 27h	global data initialization complete
 28h	post-interrupt-vector-initialization initialization complete
 29h	monochrome mode set
 2Ah	color mode set
 2Bh	parity toggle on option video ROM test complete
 2Ch	initialization before video ROM control complete
 2Dh	video ROM check complete
 2Eh	!!!
 A9h	returned from E0000h adapter ROM
 AAh	final initializations after adapter ROM initializations complete
SeeAlso: #P0411,#P0412,#P0413

(Table P0411)
Values for AWARD (non-PnP) diagnostic code:
 01h	Processor Test 1
 02h	Processor Test 2
 03h	initialize chips
 04h	test memory refresh toggle
 05h	blank video, initialize keyboard
 06h	reserved
 07h	test CMOS and CMOS batter status
 08h	setup low memory
 09h	early cache initialization
 0Ah	interrupt vector initialization
 0Bh	test CMOS RAM checksum
 0Ch	initialize keyboard
 0Dh	initialize video interface
 0Eh	test video memory
 0Fh	test DMA channel 0
 10h	test DMA channel 1
 11h	test DMA page registers
 12h	reserved
 13h	reserved
 14h	test timer channel 2
 15h	test master PIC mask bits
 16h	test slave PIC mask bits
 17h	test 8259 stuck interrupt bits
 18h	test 8259 interrupt functionality
 19h	test for stuck NMI
 1Ah	display CPU clock
 1Bh-1Eh reserved
 1Fh	set EISA mode
 20h	enable Slot 0 (system board)
 21h-2Fh enable Slots 1-15
 30h	get base and extended memory size
 31h	test base and extended memory
 32h	test EISA memory
 33h-3Bh reserved
 3Ch	set allow-setup flag
 3Dh	initialize / install mouse
 3Eh	initialize cache controller
 3Fh	reserved
 41h	initialize floppy controller and drives
 42h	initialize hard disk controller and drives
 43h	detect / initialize serial and parallel ports
 44h	reserved
 45h	initialize math coprocessor
 46h-4Dh reserved
 4Eh	Manufacturing Post loop / or / display any error messages
 4Fh	ask for password, if enabled
 50h	update CMOS RAM
 51h	pre-boot enable of parity, NMI, cache
 52h	initialize option ROMs
 53h	initialize BIOS time from RTC
 60h	setup boot-sector protection
 61h	set boot CPU speed
 62h	setup NumLock
 63h	attempt to boot via INT 19h
 B0h	spurious interrupt while in protected mode
 B1h	unclaimed NMI
 BEh	chipset default initialization
 BFh	chipset initialization
 C0h	turn off chipset cache
 C1h	check on-board memory size
 C5h	early shadow-RAM enable for faster boot
 C6h	detect external cache size
 E1h-EFh setup utility pages 1-15
 FFh	system booting operating system
SeeAlso: #P0410,#P0412,#P0413

(Table P0412)
Values for AWARD (Plug-and-Play) POST code:
 01h-02h reserved
 03h	initialize EISA register (if applicable)
 04h	reserved
 05h	keyboard controller test, initialize keyboard
 06h	reserved
 07h	test CMOS and CMOS batter status
 09h	program Cyrix CPU configuration; OEM-specific cache initialization
 0Ah	initialize interrupt vectors; early power management initialization
 0Bh	check CMOS RAM; assign I/O and memory to PCI devices
 0Ch	initialize BIOS data area
 0Dh	early chipset setup; measure CPU speed; video initialization
 0Eh	display Award logo, OEM-specific sign-on messages
 0Fh	test DMA channel 0
 10h	test DMA channel 1
 11h	test DMA page registers
 12h-13h reserved
 14h	test timer channel 2
 15h	test master PIC mask bits
 16h	test slave PIC mask bits
 17h	reserved
 19h	test 8259 functionality
 1Ah-1Dh reserved
 1Eh	EISA initialization (if applicable and EISA NVRAM checksum is good)
 1Fh-29h reserved
 30h	get base and extended memory size
 31h	test base and extended memory
 32h	program on-board serial/parallel ports, floppy controller
 33h-3Bh reserved
 3Ch	set allow-setup flag
 3Dh	initialize keyboard, install PS/2 mouse if attached
 3Eh	try to turn on L2 cache
 3Fh-40h reserved
 41h	initialize floppy controller, drives
 42h	initialize hard disk controller, drives
 43h	initialize serial/parallel ports (if PnP)
 44h	reserved
 45h	initialize math coprocessor
 46h-4Dh reserved
 4Eh	display any error messages
 4Fh	ask for password, if required
 50h	update CMOS RAM
 51h	reserved
 52h	initialize expansion ROMs, PCI, PnP, shadow RAM, power management
 53h	if not PnP, initialize serial/parallel ports; set BIOS time
 54h-5Fh reserved
 60h	set boot-sector protection
 61h	turn on L2 cache; set boot speed; final chipset/PM initialization
 62h	setup daylight savings time; set NumLock, typematic
 63h	update ESCD (PnP only) if changes; boot system via INT 19h
 B0h	spurious interrupt while in protected mode
 B1h	unclaimed NMI
 BEh	chipset default initialization
 BFh	chipset initialization
 C0h	turn off chipset cache, init DMA/PIC/timer/RTC with default values
 C1h	check on-board DRAM and cache size
 C3h	test first 256K DRAM, expand compressed BIOS image into DRAM
 C5h	early shadow-RAM enable for faster boot
 FFh	system is booting operating system
SeeAlso: #P0410,#P0411,#P0413

(Table P0413)
Values for Chips&Technologies 82C100/82C235 POST code:
 01h	flags register failed
 02h	a CPU register failed
 03h	incorrect ROM checksum
 04h	DMA controller failed
 05h	system timer failed
 06h	first 64K of RAM failed address test
 07h	first 64K of RAM failed RAM test
 08h	interrupt controller failed
 09h	"Hot Interrupt" occurred
 0Ah	reserved
 0Bh	CPU still in protected mode
 0Ch	DMA page register failed
 0Dh	no RAM refresh
 0Eh	no response from keyboard controller
 0Fh	unable to enter protected mode
 10h	GDT or IDT register failed
 11h	LDT register failed
 12h	task register failed
 13h	LSL instruction failed
 14h	LAR instruction failed
 15h	VERR or VERW instruction failed
 16h	keyboard controller A20 gate failed
 17h	exception failed, or shutduwon on unexpected exception
 18h	shutdown during memory test
 19h	checksum error in copyright string
 1Ah	BMS checksum error
---POST progress codes---
 50h	initialize hardware
 51h	initialize timer
 52h	initialize DMA controller
 53h	initialize 8259
 54h	initialize chipset
 55h	reserved
 56h	first entry into protected mode
 57h	memory-chip sizing
 58h	reserved
 59h	first exit from protected mode
 5Ah	system-board memory size determination
 5Bh	shadow RAM relocation
 5Ch	configure possible EMS
 5Dh	reserved
 5Eh	re-test lowest 64K of RAM
 5Fh	test shadow RAM
 60h	test CMOS RAM
 61h	test video
 63h	test protected mode interrupts
 64h	test A20
 65h	memory address line tests
 66h	test base memory
 67h	test extended memory
 68h	test timer interrupt
 69h	test real-time clock
 6Ah	test keyboard controller
 6Bh	test 80287
 6Ch	test RS232
 6Dh	test parallel port
 6Eh	reserved
 6Fh	test floppy disk controller
 70h	test fixed disk controller
 71h	test keylock
 72h	test mouse / pointing device
 73h-8Fh reserved
 90h	setup RAM
 91h	determine CPU speed
 92h	configuration check
 93h	initialize BIOS
 94h	POD bootstrap
 95h	reset ICs
 96h	setup cache controller
SeeAlso: #P0410,#P0411,#P0412,#P0414,#P1017

(Table P0414)
Values for Intel SE440BX ("Seattle") motherboard POST codes:
 02h	verify real mode
 03h	disable NMI
 04h	CPU type determination
 06h	system hardware initialization
 08h	chipset initialization (initial POST values)
 09h	set IN-POST flag
 0Ah	CPU register initialization
 0Bh	enable CPU cache
 0Ch	cache initialization (initial POST values)
 0Eh	I/O component initialization
 0Fh	local-bus IDE initialization
 10h	power management initialization
 11h	load alternate rgisters with initial POST values
 12h	warm boot: restore CPU control word
 13h	PCI bus-mastering device initialization
 14h	keyboard controller initialization
 16h	checksum BIOS ROM
 17h	cache initialization (before memory autosizing)
 18h	initialize 8254 timer
 1Ah	8237 DMA controller initialization
 1Ch	programmable interrupt controller reset
 20h	DRAM refresh test
 22h	keyboard controller test
 24h	ES register set to 4G flat
 26h	A20 enabled
 28h	DRAM autosizing
 29h	POST memory manager initialization
 2Ah	512K base RAM cleared
 2Ch	RAM failure on address line xxxx
 2Eh	RAM failure on data bits xxxx of memory bus low byte
 2Fh	cache enabled before system BIOS shadowing
 30h	RAM failure on data bits xxxx of memory bus high byte
 32h	CPU bus-clock frequency test
 33h	POST dispatch manager initialization
 34h	CMOS RAM test
 35h	alternate chipset register initialization
 36h	warm start shutdown
 37h	chipset reinitialization (motherboard)
 38h	system BIOS ROM shadowing
 39h	cache reinitialization (motherboard)
 3Ah	cache autosizing
 3Ch	advanced chipset register configuration
 3Dh	load alternate registers with CMOS values
 40h	initial CPU speed set
 42h	interrupt vector initialization
 44h	BIOS interrupt initialization
 45h	POST device initialization
 46h	ROM copyright notice check
 47h	PCI option ROM manager initialization
 48h	check video configuration against CMOS RAM data
 49h	PCI bus and device initialization
 4Ah	video adapter initialization
 4Bh	display QuietBoot screen
 4Ch	vidoe BIOS ROM shadowing
 4Eh	display BIOS copyright notice
 50h	display CPU type and speed
 51h	EISA motherboard initialization
 52h	keyboard test
 54h	set key click (if enabled)
 56h	enable keyboard
 58h	test for unexpected interrupts
 59h	POST display service initialization
 5Ah	display prompt "Press F2 to enter SETUP"
 5Bh	disable CPU cache
 5Ch	RAM test (512K-640K)
 60h	extended memory test
 62h	extended memory address line test
 64h	jump to UserPatch1
 66h	advanced cache register configuration
 67h	multiprocessor APIC initialization
 68h	enable L1 and L2 caches
 69h	SMM area setup
 6Ah	display L2 cache size
 6Ch	display	shadow-area message
 6Eh	display possible UMB recovery high address
 70h	display error messages
 72h	configuration error check
 74h	real-time clock test
 76h	keyboard-error check
 7Ah	test for key lock on
 7Ch	hardware interrupt vector setup
 7Eh	coprocessor initialization (if present)
 80h	disable onboard SuperI/O ports and IRQs
 81h	late POST device initialization
 82h	detect/install external serial ports
 83h	non-MCD IDE controller configuration
 84h	detect/install external parallel ports
 85h	PC-compatible PnP ISA device initialization
 86h	onboard I/O port reinitialization
 87h	configure motherboard configurable devices
 88h	BIOS data area initialization
 89h	enable NMI
 8Ah	extended BIOS data area initialization
 8Bh	test/initialize PS/2 mouse
 8Ch	diskette controller initialization
 8Fh	determine number of ATA drives
 90h	hard-disk controller initialization
 91h	local-bus hard-disk controller initialization
 92h	jump to UserPatch2
 93h	build MPTABLE for multiprocessor boards
 94h	disable A20 (Release 5.1 and earlier)
 95h	install CD-ROM for boot
 96h	clear ES 4G segment register
 97h	multiprocessor table fixup
 98h	option ROM search
 99h	check for SMART drive
 9Ah	option ROM shadowing
 9Ch	power management setup
 9Eh	enable hardware interrupts
 9Fh	determine number of ATA and SCSI devices
 A0h	set time of day
 A2h	check key lock
 A4h	typematic rate initialization
 A8h	erase F2 prompt
 AAh	test for F2 keystroke
 ACh	enter SETUP
 AEh	clear IN-POST flag
 B0h	check for errors
 B2h	preparing to boot OS - POST complete
 B4h	short beep before booting
 B5h	terminate QuietBoot
 B6h	password check (optional)
 B8h	clear global descriptor table
 B9h	clean up all graphics
 BAh	DMI parameter initialization
 BBh	PnP option ROM initialization
 BCh	clear parity checkers
 BDh	display MultiBoot menu
 BEh	clear screen (optional)
 BFh	check virus and backup reminders
 C0h	INT 19 boot attempt
 C1h	POST Error Manager (PEM) initialization
 C2h	error logging initialization
 C3h	error display function initialization
 C4h	system error handler initialization
 E0h	chipset initialization
 E1h	bridge initialization
 E2h	processor initialization
 E3h	system timer initialization
 E4h	system I/O initialization
 E5h	check force recovery boot
 E6h	BIOS ROM checksumming
 E7h	go to BIOS
 E8h	set huge segment
 E9h	multiprocessor initialization
 EAh	OEM special code initialization
 EBh	PIC and DMA initialization
 ECh	memory type initialization
 EDh	memory size initialization
 EEh	boot block shadowing
 EFh	system memory test
 F0h	interrupt vector initialization
 F1h	real-time clock initialization
 F2h	video initialization
 F3h	beeper initialization
 F4h	initialize boot
 F5h	clear huge segment
 F6h	boot to mini-DOS
 F7h	boot to full DOS
SeeAlso: #P0413,#P1017

(Table P1017)
Values for Microid Research MR-BIOS POST codes:
 00h	starting cold boot
 01h	OEM-specific hook #0 (typically chipset reset)
 02h	disable critical I/O devices (6845, 8327s, floppy, and parity latches)
 03h	BIOS checksum test (beep code LH-LLL; L=low tone, H=high tone)
 04h	test page registers (PORT 0081h-008Fh) (beep code LH-HLL)
 05h	keyboard controller self-test (beep code LH-LHL)
 06h	gang port initialization (both 8237s, both 7254s, RTC registers
	  0Fh/0Ah, and both 8259s)
 07h	OEM-specific hook #1 (typically cache and shadow RAM disable)
 08h	test refresh toggle (beep code LH-HHL)
 09h	pattern test both 8237s (beep code LH-LLH)	
 0Ah	test first 64K RAM (beep code LH-LLLL or LH-HLLL)
 0Bh	pattern test both 8259s mask registers
	(beep code LH-HHHL [master] or LH-LLLH [slave])
 0Ch	test 8259 IRQs and purge powerup interrupts
 0Dh	test and init 8254 channel 0
 0Eh	test 8254 channel 2 and speaker circuitry
 0Fh	test and init RTC
 10h	initialize video
 11h	text CMOS checksum
 12h	display signon message, accept keyboard selftest result, attempt
	  to initialize keyboard
 13h	OEM-specific hook #2 (typically 8MHz-bus select)
 14h	size and test base memory
 15h	second attempt to initialize keyboard, if necessary
 16h	OEM-specific hook #3 (typically cache sizing/test)
 17h	test A20 gate
 18h	size and test extended memory
 19h	OEM-specific hook #4 (size/test "special" OEM memory)
 1Ah	test RTC update-in-progress flag and validate time
 1Bh	determine serial ports
 1Ch	determine parallel ports
 1Dh	determine/initialize coprocessor
 1Eh	floppy controller test/determination and CMOS validation
 1Fh	determine/test fixed disk controller, validate CMOS settings
 20h	rigorous CMOS parameter validation
 21h	check frnot-panel lock, wait for user acknowledgement of errors
 22h	set NumLock, password-security trap, dispatch to setup utility
 23h	OEM-specific hook #5
 24h	set keyboard typematic rate
 25h	initialize floppy subsystem
 26h	initialize fixed-disk subsystem
 27h	ACK errors, set primary adapter's video mode
 28h	OEM-specific hook #6 (typically enable shaow RAM, cache, turbo mode)
 29h	disable A20, set low stack, init ROMs at C800-E000
 2Ah	ACK errors, set video mode, set DOS time from RTC
 2Bh	enable parity checking and NMI
 2Ch	init ROM at E000
 2Dh	ACK errors
 2Eh	OEM-specific hook #7 (typically init built-in EMS)
 2Fh	passing control to INT 19h
SeeAlso: #0410,#0414

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P0080008F - PORT 0080-008F - DMA PAGE REGISTERS (74612)

PORT 0080-008F - DMA PAGE REGISTERS (74612)

0080  RW  extra page register (temporary storage)
0081  RW  DMA channel 2 address byte 2
0082  RW  DMA channel 3 address byte 2
0083  RW  DMA channel 1 address byte 2
0084  RW  extra page register
0085  RW  extra page register
0086  RW  extra page register
0087  RW  DMA channel 0 address byte 2
0088  RW  extra page register
0089  RW  DMA channel 6 address byte 2
008A  RW  DMA channel 7 address byte 2
008B  RW  DMA channel 5 address byte 2
008C  RW  extra page register
008D  RW  extra page register
008E  RW  extra page register
008F  RW  DMA refresh page register

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P0080009F - PORT 0080-009F - Intel386sx CHIPSET 82231

PORT 0080-009F - Intel386sx CHIPSET 82231
Note:	includes the DMA controller functionality on PORT 0080h to PORT 008Fh

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P0084 - PORT 0084 - Compaq POST Diagnostic

PORT 0084 - Compaq POST Diagnostic

Top

P0084 - PORT 0084 - EISA - SYNCHRONIZE BUS CYCLE

PORT 0084 - EISA - SYNCHRONIZE BUS CYCLE

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P00850086 - PORT 0085-0086 - Intel "Triton" chipset - ???

PORT 0085-0086 - Intel "Triton" chipset - ???
SeeAlso: PORT 00EBh"Triton"

0085  ?W  ???
0086  ?W  ???

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P0090009F - PORT 0090-009F - PS/2 - POS (PROGRAMMABLE OPTION SELECT)

PORT 0090-009F - PS/2 - POS (PROGRAMMABLE OPTION SELECT)

0090  ??  Central arbitration control port
0090  RW  POST diagnostic code (most PS/2 with ISA bus)
0091  R-  Card selection feedback
	    bit 0 set when adapter addressed and responds, cleared on read
0092  RW  PS/2 system control port A  (port B is at PORT 0061h) (see #P0415)
0094  -W  system board enable/setup register (see #P0416)
0095  --  reserved
0096  -W  adapter enable / setup register (see #P0417)
0097  --  reserved

Bitfields for PS/2 system control port A:
Bit(s)	Description	(Table P0415)
 7-6	any bit set to 1 turns activity light on
 5	unused
 4	watchdog timout occurred
 3	=0 RTC/CMOS security lock (on password area) unlocked
	=1 CMOS locked (done by POST)
 2	unused
 1	A20 is active
 0	=0 system reset or write
	=1 pulse alternate reset pin (high-speed alternate CPU reset)
Notes:	once set, bit 3 may only be cleared by a power-on reset
	on at least the C&T 82C235, bit 0 remains set through a CPU reset to
	  allow the BIOS to determine the reset method
	on the PS/2 30-286 & "Tortuga" the INT 15h/87h memory copy does
	  not use this port for A20 control, but instead uses the keyboard
	  controller (8042). Reportedly this may cause the system to crash
	  when access to the 8042 is disabled in password server mode
	  (see #P0398).
SeeAlso: #P0416,#P0417,MSR 00001000h

Bitfields for PS/2 system board enable/setup register:
Bit(s)	Description	(Table P0416)
 7	=1  enable functions
	=0  setup functions
 5	=1  enables VGA
	=0  setup VGA
 2	=1  enable integrated SCSI (PS/2 M77)
	=0  setup integrated SCSI
SeeAlso: #P0415,#P0417

Bitfields for PS/2 adapter enable/setup register:
Bit(s)	Description	(Table P0417)
 7	activate Channel Reset on all slots
 6-4	unused (1)
 3	=1  setup adapter specified by bits 2-0
	=0  enable registers
 2-0	adapter slot select (000 = slot 1 ... 111 = slot 8)
SeeAlso: #P0416

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P00A000AF - PORT 00A0-00AF - PIC 2 - PROGRAMMABLE INTERRUPT CONTROLLER (8259A)

PORT 00A0-00AF - PIC 2 - PROGRAMMABLE INTERRUPT CONTROLLER (8259A)
SeeAlso: PORT 0020h-003Fh"PIC 1",INT 70"IRQ8",INT 77"IRQ15"

00A0  RW  PIC 2	 same as 0020 for PIC 1
00A1  RW  PIC 2	 same as 0021 for PIC 1 except for OCW1 (see #P0418)

Bitfields for PIC2 output control word OCW1:
Bit(s)	Description	(Table P0418)
 7	disable IRQ15 (reserved)
 6	disable IRQ14 (fixed disk interrupt)
 5	disable IRQ13 (coprocessor exception interrupt)
 4	disable IRQ12 (mouse interrupt)
 3	disable IRQ11 (reserved)
 2	disable IRQ10 (reserved)
 1	disable IRQ9  (redirect cascade)
 0	disable IRQ8  (real-time clock interrupt)
SeeAlso: #P0014

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P00A0 - PORT 00A0 - XT - NMI MASK REGISTER

PORT 00A0 - XT - NMI MASK REGISTER
SeeAlso: PORT 0070h,INT 02

00A0  RW  NMI mask register (XT only)
	 bit 7 = 0 NMI signal disabled from reaching CPU
	       = 1 NMI signal enabled

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P00A000AF - PORT 00A0-00AF - Chips&Technologies 82C100/110 - NMI CONTROL

PORT 00A0-00AF - Chips&Technologies 82C100/110 - NMI CONTROL
SeeAlso: PORT 0072h"82C100",PORT 007Fh"82C100"

00A0  RW  NMI mask register (XT only)
	 bit 7 = 0 NMI signal disabled from reaching CPU
	       = 1 NMI signal enabled
00Ax  RW  mirrors of PORT 00A0h

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P00A800A9 - PORT 00A8-00A9 - Via VT82C496G "Pluto" - CONFIGURATION REGISTERS

PORT 00A8-00A9 - Via VT82C496G "Pluto" - CONFIGURATION REGISTERS
SeeAlso: PORT 00A8h"VT82C570M"

00A8  ?W  configuration register index (see #P0419)
00A9  RW  configuration register data

(Table P0419)
Values for Via VT82C496G configuration registers:
 02h	clock throttling control (see #P0420)
 03h	I/O recovery (see #P0421)
 10h	bus speed (see #P0422)
 11h	ISA bus clock frequency control (see #P0423)
 20h	pair 0/1 row/column address (see #P0424)
 21h	pair 2/3 row/column address (see #P0425)
 22h	RAS#/CAS# pulse control (see #P0426)
 30h	C0000h-CFFFFh shadow control (see #P0427)
 31h	D0000h-DFFFFh shadow control (see #P0428)
 32h	E0000h-FFFFFh shadow control (see #P0429)
 33h	ROM decoding and memory relocation (see #P0430)
 40h	ROM cacheable control (see #P0431)
 41h	programmable non-cacheable region ???
 42h	programmable non-cacheable region ???
 43h	pair 0/1 DRAM size and configuration (see #P0432)
 44h	pair 2/3 DRAM size and configuration (see #P0433)
 50h	cache access mode (see #P0434)
 51h	cache timing/size control (see #P0435)
 52h	primary idle timer reloading control (see #P0436)
 53h	primary idle timer reload distinguish (see #P0437)
 54h	SMI triggering control (see #P0438)
 55h	SMI trigger distinguish (see #P0439)
 56h	clock frequency control (see #P0440)
 57h	peripheral timer (see #P0441)
 58h	general purpose timer (see #P0442)
 59h	timer control (see #P0443)
 5Ah	power/peripheral control (see #P0444)
 5Bh	system management control (see #P0445)
 5Ch	clock switching control (see #P0446)
 5Dh	peripheral timer control (see #P0447)
 5Eh	misc. cache control (see #P0448)
 5Fh	conserve mode/secondary idle timer control (see #P0449)
 60h	IRQ7-0 primary interrupt selection (see #P0450)
 61h	IRQ15-8 primary interrupt selection (see #P0451)
 62h	IRQ7-3 interrupt mode and global control (see #P0452)
 63h	IRQ15-9 interrupt mode (see #P0453)
 64h	(see #P0454)
 65h	peripheral timer control (see #P0455)
 68h	port 070h write shadow
 69h	port 2F8h write shadow
 6Ah	port 3F8h write shadow
 6Bh	port 372h write shadow
 6Ch	port 377h write shadow
 6Dh	port 171h write shadow
 6Eh	port 177h write shadow
 6Fh	port 376h write shadow
 71h	IDE controller/cache control (see #P0456)
 72h	non-1F0/170h port access timing (see #P0457)
 73h	drive #0 read timing for 1F0/170h access (see #P0458)
 74h	drive #0 write timing for 1F0/170h access (see #P0459)
 77h	drive #0 address setup time (see #P0460)
 78h	drive #1 read timing for 1F0/170h access (see #P0458)
 79h	drive #1 write timing for 1F0/170h access (see #P0459)
 7Ch	drive #1 address setup time (see #P0460)
SeeAlso: #P0461

Bitfields for Via VT82C496G/VT82C570M clock throttling control:
Bit(s)	Description	(Table P0420)
 4	STPCLK# throttling period (enabled by register 5Bh bit 0)
	0 = 3.35 æs * 16
	1 = 1.7 ms * 16
 3-0	duty cycle for STPCLK# (1/16 - 15/16) (enabled by register 5Bh bit 0)
SeeAlso: #P0419,#P0445

Bitfields for Via VT82C496G/VT82C570M register 03h:
Bit(s)	Description	(Table P0421)
 7-1	(VT82C496G) command delay, wait state and I/O recovery time for normal
	  ISA cycles ???
 0	decoupled DRAM refresh enable
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M register 10h:
Bit(s)	Description	(Table P0422)
 6	DMA controller runs at ISA clock speed/half ISA clock speed
SeeAlso: #P0419,#P0423

Bitfields for Via VT82C496G/VT82C570M ISA bus clock frequency control:
Bit(s)	Description	(Table P0423)
 6	flash EPROM write cycle support enable
 3-0	ISA bus clock frequency
	0xxx = CLKIN / 8
	1000 = CLKIN / 3
	1001 = CLKIN / 2
	1010 = CLKIN / 4
	1011 = CLKIN / 6
	1100 = CLKIN / 5
	1101 = CLKIN / 10
	1110 = CLKIN / 12
	1111 = OSC / 2 (asynchronous)
SeeAlso: #P0419,#P0422

Bitfields for Via VT82C496G/VT82C570M pair 0/1 row/column address:
Bit(s)	Description	(Table P0424)
 7-5	number of column address bits for pair 0
	000 = disabled
	001 = 9 bit
	010 = 10 bit
	011 = 11 bit
	100 = 12 bit
	101-111 = illegal
 4	page mode operation enable
 3-1	number of column address bits for pair 1 (same values as above)
 0	(VT82C496G) reserved
	(VT82C570M) DRAM bus width
	0 = 32 bit
	1 = 64 bit (operation width set in register 48h bits 3-0)
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M pair 2/3 row/column address:
Bit(s)	Description	(Table P0425)
 7-5	number of column address bits for pair 2
	000 = disabled
	001 = 9 bit
	010 = 10 bit
	011 = 11 bit
	100 = 12 bit
	101-111 = illegal
 4	reserved
 3-1	number of column address bits for pair 3 (same values as above)
 0	reserved
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M RAS#/CAS# pulse control:
Bit(s)	Description	(Table P0426)
 7-6	RAS# precharge time
	00-11 = (VT82C496G) 1-4 cycles
		(VT82C570M) 2-8 cycles
 5-4	RAS# pulse width
	00-11 = (VT82C496G) 2-5 cycles
		(VT82C570M) 4-10 cycles
 3-2	read cycle CAS# pulse width
	00-11 = 1-4 cycles
 1	write cycle CAS# pulse width
	0 = 1 cycle
	1 = 2 cycles
 0	RAS# to column address/column address to CAS#
	0 = 1 cycle
	1 = 2 cycles
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M C0000h-CFFFFh shadow control:
Bit(s)	Description	(Table P0427)
 7	CC000h-CFFFFh read shadow enable
 6	CC000h-CFFFFh write shadow enable
 5	C8000h-CBFFFh read shadow enable
 4	C8000h-CBFFFh write shadow enable
 3	C4000h-C7FFFh read shadow enable
 2	C4000h-C7FFFh write shadow enable
 1	C0000h-C3FFFh read shadow enable
 0	C0000h-C3FFFh write shadow enable
SeeAlso: #P0419,#P0428,#P0429

Bitfields for Via VT82C496G/VT82C570M D0000h-DFFFFh shadow control:
Bit(s)	Description	(Table P0428)
 7	DC000h-DFFFFh read shadow enable
 6	DC000h-DFFFFh write shadow enable
 5	D8000h-DBFFFh read shadow enable
 4	D8000h-DBFFFh write shadow enable
 3	D4000h-D7FFFh read shadow enable
 2	D4000h-D7FFFh write shadow enable
 1	D0000h-D3FFFh read shadow enable
 0	D0000h-D3FFFh write shadow enable
SeeAlso: #P0419,#P0427,#P0429

Bitfields for Via VT82C496G/VT82C570M E0000h-FFFFFh shadow control:
Bit(s)	Description	(Table P0429)
 7	E0000h-EFFFFh read shadow enable
 6	E0000h-EFFFFh write shadow enable
 5	F0000h-FFFFFh read shadow enable
 4	F0000h-FFFFFh write shadow enable
 3	???
 2	memory range F00000h-FFFFFFh decode as ISA cycle enable
 1	(VT82C496G) burstable DRAM cycles enable
	(VT82C570M) ???
 0	???
SeeAlso: #P0419,#P0427,#P0428,#P0430

Bitfields for Via VT82C496G/VT82C570M ROM decoding and memory relocation:
Bit(s)	Description	(Table P0430)
 7	C8000h-CFFFFh decoded as ROM cycle enable
 6	C0000h-C7FFFh decoded as ROM cycle enable
 5	E8000h-EFFFFh decoded as ROM cycle enable
 4	E0000h-E7FFFh decoded as ROM cycle enable
 3-2	memory relocation
	00 = disable
	01 = illegal
	10 = 256K relocation
	11 = 384K relocation
 1	(VT82C496G) RAS time-out
	(VT82C570M) ???
 0	???
SeeAlso: #P0419,#P0429,#P0431

Bitfields for Via VT82C496G/VT82C570M ROM cacheable control:
Bit(s)	Description	(Table P0431)
 7	C0000h-C7FFFh cacheable and write-protect enable
 6	F0000h-FFFFFh cacheable and write-protect enable
 5	E0000h-EFFFFh cacheable and write-protect enable
 4	???
 3	CAS-to-RAS refresh enable
 2	(VT82C570M) secondary cache fill for CACHE# inactive memory cycles
	  enable
 1-0	???
SeeAlso: #P0419,#P0430

Bitfields for Via VT82C496G/VT82C570M pair 0/1 DRAM size and configuration:
Bit(s)	Description	(Table P0432)
 7-5	(VT82C496G) bank-pair 0 DRAM size (x2 if double bank)
	000 = 512 KB
	001 = 1 MB
	010 = 2 MB
	011 = 4 MB
	100 = 8 MB
	101 = 16 MB
	110 = 32 MB
	111 = 64 MB
	(VT82C570M) bank-pair 0 DRAM size (x2 if double bank)
	000 = 1 MB
	001 = 2 MB
	010 = 4 MB
	011 = 8 MB
	100 = 16 MB
	101 = 32 MB
	110 = 64 MB
	111 = 128 MB
 4	number of banks in pair 0
	(0 bank if register 20h bit 7-5 = 0)
	0 = 1 bank
	1 = 2 banks
 3-1	(VT82C496G) bank-pair 1 DRAM size (x2 if double bank)
	(VT82C570M) bank-pair 1 DRAM size (x2 if double bank)
 0	number of banks in pair 1
	(0 bank if register 20h bit 3-1 = 0)
	0 = 1 bank
	1 = 2 banks
SeeAlso: #P0419,#P0433

Bitfields for Via VT82C496G/VT82C570M pair 2/3 DRAM size and configuration:
Bit(s)	Description	(Table P0433)
 7-5	(VT82C496G) bank-pair 2 DRAM size (x2 if double bank)
	000 = 512 KB
	001 = 1 MB
	010 = 2 MB
	011 = 4 MB
	100 = 8 MB
	101 = 16 MB
	110 = 32 MB
	111 = 64 MB
	(VT82C570M) bank-pair 2 DRAM size (x2 if double bank)
	000 = 1 MB
	001 = 2 MB
	010 = 4 MB
	011 = 8 MB
	100 = 16 MB
	101 = 32 MB
	110 = 64 MB
	111 = 128 MB
 4	number of banks of pair 2 (no banks if register 21h bit 7-5 = 0)
	0 = 1 bank
	1 = 2 banks
 3-1	(VT82C496G) bank-pair 3 DRAM size (x2 if double bank)
	(VT82C570M) bank-pair 3 DRAM size (x2 if double bank)
	(same values as for bits 7-5)
 0	number of banks of pair 3 (no banks if register 21h bit 3-1 = 0)
	0 = 1 bank
	1 = 2 banks
SeeAlso: #P0419,#P0432

Bitfields for Via VT82C496G/VT82C570M cache access mode:
Bit(s)	Description	(Table P0434)
 7-6	cache mode
	0x = disabled
	10 = enabled
	11 = initialization
 5	(VT82C496G) direct data SRAM access
	(VT82C570M) Cyrix CPU linear burst order enable
 4	(VT82C496G) write-back cache alter bit control (don't care for write
	  through)
	0 = combined tag/alter bit
	1 = no alter bit
 4-3	(VT82C570M) number of tag/alter bits
	  write-back (register 5Eh bit 6 = 0)
	       tag   alter   total
	  00	 8	 0	 8
	  01	 7	 1	 8
	  10	 8	 1	 9
	  11	10	 1	11
	  write-through (register 5Eh bit 6 = 1)
	       tag   alter   total
	  x0	 8	 -	 8
	  01	 7	 -     N/A
	  11	10	 -	10
 3-2	(VT82C496G) cache line size
	00 = 4 bytes
	01 = 8 bytes
	10 = 16 bytes
	11 = 4 bytes
 2	(VT82C570M) data synchronous SRAM type (if register 51h bit 4 = 0)
	0 = standard synchronous SRAM
	1 = pipelined burst synchronous SRAM
 1	(VT82C496G) burst write enable
	(VT82C570M) cache read wait state for PCI masters (PCI clock)
	0 = zero wait state (2-1-1-1)
	1 = one wait state (3-2-2-2)
 0	(VT82C496G) data streaming enable
	(VT82C570M) cache write wait state for PCI masters (PCI clock)
	0 = zero wait state (2-1-1-1)
	1 = one wait state (3-2-2-2)
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M cache timing/size control:
Bit(s)	Description	(Table P0435)
 7	(VT82C496G) read hit timing
	0 = 2-X-X-X
	1 = 3-X-X-X
	(VT82C570M) read hit timing for first cycle (CPU clock) for
	  asynchronous SRAM
	0 = 1 wait state (2-X-X-X)
	1 = 2 wait state (3-X-X-X)
 6	(VT82C496G) write hit timing
	0 = 2-X-X-X
	1 = 3-X-X-X
	(VT82C570M) write hit timing for first cycle (CPU clock) for
	  asynchronous SRAM
	0 = 1 wait state (3-X-X-X)
	1 = 2 wait state (4-X-X-X)
 5	(VT82C496G) read hit timing
	0 = X-1-1-1
	1 = X-2-2-2
	(VT82C570M) read hit timing for second-fourth burst cycle (CPU clock)
	  for asynchronous SRAM
	0 = 1 wait state (X-2-2-2)
	1 = 2 wait state (X-3-3-3)
 4	(VT82C496G) write hit timing
	0 = X-1-1-1
	1 = X-2-2-2
	(VT82C570M) data SRAM type
	0 = synchronous SRAM (type set in register 50h bit 2)
	1 = asynchronous SRAM
 3	bank of data SRAM
	0 = 1 bank
	1 = 2 banks
 2-0	cache size
	000 = no cache
	001 = (VT82C496G) 32 KB
	010 = (VT82C496G) 64 KB
	011 = 128 KB
	100 = 256 KB
	101 = 512 KB
	110 = 1 MB
	111 = (VT82C570M) 2 MB
Note:	(VT82C570M) write hit timing is always 1 wait state (X-2-2-2) for
	  asynchronous SRAM; read/write hit timing is always 3-1-1-1 for
	  synchronous SRAM
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M primary idle timer reloading control:
Bit(s)	Description	(Table P0436)
 7	reload primary idle timer on keyboard access
 6	reload primary idle timer on serial port access
 5	reload primary idle timer on parallel port access
 4	reload primary idle timer on video access
 3	reload primary idle timer on hard disk and floppy access
 2	reload primary idle timer on IO port 100h-3FFh access
 1	reload primary idle timer on external input
 0	reload primary idle timer on DRQ/LREQ (DMA/local bus master request)
SeeAlso: #P0419,#P0437,#P0438

Bitfields for Via VT82C496G/VT82C570M primary idle timer reload distinguish:
Bit(s)	Description	(Table P0437)
 7	primary idle timer reloaded by keyboard access
 6	primary idle timer reloaded by serial port access
 5	primary idle timer reloaded by parallel port access
 4	primary idle timer reloaded by video access
 3	primary idle timer reloaded by hard disk and floppy access
 2	primary idle timer reloaded by IO port 100h-3FFh access
 1	primary idle timer reloaded by external input
 0	primary idle timer reloaded by DRQ/LREQ (DMA/local bus master request)
SeeAlso: #P0419,#P0436,#P0438

Bitfields for Via VT82C496G/VT82C570M SMI triggering control:
Bit(s)	Description	(Table P0438)
 7	trigger SMI on primary idle timer time-out
 6	trigger SMI on general purpose timer time-out
 5	trigger SMI on primary activity occurrence
 4	trigger SMI on primary interrupt occurrence
 3	trigger SMI on external pin (Turbo) toggle
 2	(VT82C496G) trigger SMI on DRQ/LREQ occurrence
	(VT82C570M) trigger SMI on DRQ/PREQ occurrence
 1	trigger SMI on peripheral timer or secondary idle timer
	  time-out
	(VT82C496G) (use register 65h bits 3 and 2 to distinguish)
 0	trigger SMI on software SMI
SeeAlso: #P0419,#P0436,#P0438,#P0439

Bitfields for Via VT82C496G/VT82C570M SMI trigger distinguish:
Bit(s)	Description	(Table P0439)
 7	SMI triggered by primary idle timer time-out
 6	SMI triggered by general purpose timer time-out
 5	SMI triggered by primary activity occurrence
 4	SMI triggered by primary interrupt occurrence
 3	SMI triggered by external pin (Turbo) toggle
 2	(VT82C496G) SMI triggered by DRQ/LREQ occurrence
	(VT82C570M) SMI triggered by DRQ/PREQ occurrence
 1	SMI triggered by peripheral timer or secondary idle timer
	  time-out
	(VT82C496G) (use register 65h bits 1 and 0 to distinguish)
 0	SMI triggered by software SMI
SeeAlso: #P0419,#P0438

Bitfields for Via VT82C496G/VT82C570M clock frequency control:
Bit(s)	Description	(Table P0440)
 7-5	(VT82C496G) CPU clock frequency
	000 = CLKIN
	001 = CLKIN / 4
	010 = CLKIN / 8
	011 = CLKIN / 16
	100 = CLKIN / 32
	101 = CLKIN / 64
	110 = CLKIN / 2
	111 = 0
 3-0	CLKIN frequency
	0000 = 16 MHz
	0001 = 40 MHz
	0010 = 50 MHz
	0011 = 80 MHz
	0100 = 66 MHz
	0101 = 100 MHz
	0110 = 8 MHz
	0111 = 60 MHz
	1000 = 8 MHz
	1001 = 20 MHz
	1010 = 25 MHz
	1011 = 40 MHz
	1100 = 33 MHz
	1101 = 50 MHz
	1110 = 4 MHz
	1111 = 30 MHz
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M peripheral timer:
Bit(s)	Description	(Table P0441)
 7-0	(VT82C496G) peripheral timer (time base determined in register 5Dh
	  bits 1-0)
	(VT82C570M) peripheral timer (time base determined in register 66h
	  bits 3-2)
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M general purpose timer:
Bit(s)	Description	(Table P0442)
 7-0	general purpose timer (time base determined in register 59h bits 7-6)
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M timer control:
Bit(s)	Description	(Table P0443)
 7-6	general purpose timer (register 58h) time base
	00 = disable
	01 = 32.768 KHz
	10 = 1 sec
	11 = 1 min
 3-1	primary idle timer time-out
	000 = disable
	001 = 1 sec
	010 = 8 sec
	011 = 32 sec
	100 = 1 min
	101 = 8 min
	110 = 16 min
	111 = 32 min
 0	(VT82C496G) leakage control mode
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M power/peripheral control:
Bit(s)	Description	(Table P0444)
 7-4	general purpose output ports ???
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M system management control:
Bit(s)	Description	(Table P0445)
 7	(VT82C496G) power management mode enable
 6	(VT82C496G) SMI type
	0 = Intel 2-pin SMI (SMI#/SMIACT#)
	  (pin 112 used as SMIACT#, SM base = 30000h to 4FFFFh)
	1 = TI/AMD/Cyrix 3-pin SMI (SMI#/SMIADS#/SMIRDY#)
	  (pin 112 used as SMIADS#, SM base = 60000h to 7FFFFh)
 5	(VT82C496G) SMI target
	0 = SMI output to CPU
	1 = SMI redirected to interrupt 15 of internal 8259 interrupt
	  controller (for non-SMI CPU support)
 4	SM memory remap enable (SM base memory mapped to A0000h to BFFFFh)
 3	(VT82C496G) direct DRAM access to SMI target memory A0000h-BFFFFh
	  enable
 2	???
 1	(VT82C496G) force 3000h-4FFFFh to map to A0000h-BFFFFh
	(move SM code without causing local bus device conflict with
	  A0000h-BFFFFh)
 0	clock throttling enable
SeeAlso: #P0419

Bitfields for Via VT82C496G clock switching control:
Bit(s)	Description	(Table P0446)
 7	wait for a HALT cycle to start clock switching
 6	wait for an acknowledgment to start clock switching
 5	clock switching protocol
	0 = Intel STPCLK# protocol (pin 117 used as STPCLK# output)
	1 = TI/Cyrix SUSP#/SUSPA# protocol (pin 117 used as SUSP# input)
SeeAlso: #P0419

Bitfields for Via VT82C496G peripheral timer control:
Bit(s)	Description	(Table P0447)
 7-2	???
 1-0	peripheral timer (register 57h) time base
	00 = disable
	01 = 32.768 KHz
	10 = 1 sec
	11 = 1 min
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M misc. cache control:
Bit(s)	Description	(Table P0448)
 7	(VT82C496G) CPU internal cache
	0 = write-through
	1 = write-back
 6	external cache
	0 = write-back
	1 = write-through
 5	(VT82C496G) pin 72 usage
	0 = BLAST# (burst last input from the CPU)
	1 = CACHE# (P24T) (burst cycle indicator)
 4	(VT82C496G) snoop filtering enable
 3	???
 2	slow refresh enable
 1-0	???
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M conserve mode/secondary idle timer:
Bit(s)	Description	(Table P0449)
 7-6	(VT82C496G) conserve mode active period
	00 = 1/16 sec
	01 = 1/8 sec
	10 = 1 sec
	11 = 1 min
 5	conserve mode enable
 4	(VT82C496G) conserve mode clock select
	0 = CLKIN / 2
	1 = CLKIN / 4
 3-2	secondary idle timer time-out
	00 = 2 ms
	01 = 16 ms
	10 = 64 ms
	11 = EOI + 0.125 ms
 1	secondary events handler enable (secondary interrupt reloads secondary
	  idle timer)
 0	(VT82C496G) change clock speed on secondary interrupt to
	0 = CLKIN
	1 = CLKIN / 2
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M IRQ7-0 primary interrupt selection:
Bit(s)	Description	(Table P0450)
 7	IRQ7 is primary interrupt
 6	IRQ6 is primary interrupt
 5	IRQ5 is primary interrupt
 4	IRQ4 is primary interrupt
 3	IRQ3 is primary interrupt
 2	IRQ1 is primary interrupt
 1	IRQ0 is primary interrupt
 0	(VT82C496G) reload primary idle timer on primary interrupt
SeeAlso: #P0419,#P0451,#P0452

Bitfields for Via VT82C496G/VT82C570M IRQ15-8 primary interrupt selection:
Bit(s)	Description	(Table P0451)
 7	IRQ15 is primary interrupt
 6	IRQ14 is primary interrupt
 5	IRQ13 is primary interrupt
 4	IRQ12 is primary interrupt
 3	IRQ11 is primary interrupt
 2	IRQ10 is primary interrupt
 1	IRQ9 is primary interrupt
 0	IRQ8 is primary interrupt
SeeAlso: #P0419,#P0450,#P0453

Bitfields for Via VT82C496G IRQ7-3 interrupt mode and global control:
Bit(s)	Description	(Table P0452)
 7	IRQ7 interrupt mode (refer to note below)
 6	IRQ6 interrupt mode
 5	IRQ5 interrupt mode
 4	IRQ4 interrupt mode
 3	IRQ3 interrupt mode
 2	IRQ8 treated as
	0 = sub-secondary interrupt (CPU clock speed unchanged)
	1 = secondary interrupt
 1	IRQ0 treated as
	0 = sub-secondary interrupt (CPU clock speed unchanged)
	1 = secondary interrupt
 0	interrupt mode global control
	0 = 8259A compatible mode (all interrupt edge triggered)
	1 = extended mode (enables selection with registers 62h and 63h)
Note:	for bits 7-3, 0 = edge-triggered, 1 = level-sensitive
SeeAlso: #P0419,#P0450,#P0453

Bitfields for Via VT82C496G/VT82C570M IRQ15-9 interrupt mode:
Bit(s)	Description	(Table P0453)
 7	IRQ15 interrupt mode (refer to note below)
 6	IRQ14 interrupt mode
 5	reserved
 4	IRQ12 interrupt mode
 3	IRQ11 interrupt mode
 2	IRQ10 interrupt mode
 1	IRQ9 interrupt mode
 0	???
Note:	for bits 7-6 and 4-1, 0 = edge-triggered, 1 = level-sensitive
SeeAlso: #P0419,#P0451,#P0452

Bitfields for Via VT82C496G/VT82C570M register 64h:
Bit(s)	Description	(Table P0454)
 3-0	MA0-3 jumper setting ???
SeeAlso: #P0419

Bitfields for Via VT82C496G/VT82C570M peripheral timer control:
Bit(s)	Description	(Table P0455)
 7	reload peripheral timer on keyboard access
 6	reload peripheral timer on serial port access
 5	reload peripheral timer on video access
 4	reload peripheral timer on hard disk and floppy access
 3	(VT82C496G) trigger SMI on peripheral timer time-out
	(VT82C570M) reload peripheral timer on parallel port access
 2	(VT82C496G) trigger SMI on secondary idle timer time-out
	(VT82C570M) reserved
 1	(VT82C496G) SMI triggered by peripheral timer time-out
	(VT82C570M) reload peripheral timer on speaker access
 0	(VT82C496G) SMI triggered by secondary idle timer time-out
	(VT82C570M) reserved
SeeAlso: #P0419

Bitfields for Via VT82C496G IDE controller/cache control:
Bit(s)	Description	(Table P0456)
 7	reserved
 6	channel and I/O port selection
	0 = primary channel (1F0h-1F7h)
	1 = secondary channel (170h-177h)
 5	write buffer enable
 4	prefetch buffer enable
 3	internal LRDY# for write cycles (0 = second T2, 1 = first T2)
 2	internal LRDY# for read cycles	(0 = second T2, 1 = first T2)
 1	read data to be presented to CPU data bus
	0 = second T2
	1 = first T2
 0	internal IDE controller enable
SeeAlso: #P0419

Bitfields for Via VT82C496G non-1F0/170h port access timing:
Bit(s)	Description	(Table P0457)
 7-4	number of CPU clocks as command active time
 3-0	number of CPU clocks as command recovery time
SeeAlso: #P0419

Bitfields for Via VT82C496G drive #0/1 read timing for 1F0/170h access:
Bit(s)	Description	(Table P0458)
 7-4	number of CPU clocks as command active time
 3-0	number of CPU clocks as command recovery time
SeeAlso: #P0419,#P0459,#P0460

Bitfields for Via VT82C496G drive #0/1 write timing for 1F0/170h access:
Bit(s)	Description	(Table P0459)
 7-4	number of CPU clocks as command active time
 3-0	number of CPU clocks as command recovery time
SeeAlso: #P0419,#P0458,#P0460

Bitfields for Via VT82C496G drive #0/1 address setup time:
Bit(s)	Description	(Table P0460)
 1-0	number of CPU clocks as address setup time
SeeAlso: #P0419,#P0458,#P0459

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P00A800AC - PORT 00A8-00AC - Via VT82C570M "Apollo Master" - CONFIGURATION REGISTERS

PORT 00A8-00AC - Via VT82C570M "Apollo Master" - CONFIGURATION REGISTERS
SeeAlso: PORT 00A8h"VT82C486G"

00A8  ?W  configuration register index (see #P0461)
00A9  RW  configuration register 00h-9Fh data
00AC  RW  configuration register FBh-FFh data

(Table P0461)
Values for Via VT82C570M configuration registers:
 02h	clock throttling control (see #P0420)
 03h	I/O recovery (see #P0421)
 10h	bus speed (see #P0422)
 11h	ISA bus clock frequency control (see #P0423)
 20h	pair 0/1 row/column address (see #P0424)
 21h	pair 2/3 row/column address (see #P0425)
 22h	RAS#/CAS# pulse control (see #P0426)
 30h	C0000h-CFFFFh shadow control (see #P0427)
 31h	D0000h-DFFFFh shadow control (see #P0428)
 32h	E0000h-FFFFFh shadow control (see #P0429)
 33h	ROM decoding and memory relocation (see #P0430)
 40h	ROM cacheable control (see #P0431)
 41h	programmable non-cacheable region ???
 42h	programmable non-cacheable region ???
 43h	pair 0/1 DRAM size and configuration (see #P0432)
 44h	pair 2/3 DRAM size and configuration (see #P0433)
 47h	DRAM type (see #P0462)
 48h	DRAM control (see #P0463)
 49h	cache control (see #P0464)
 50h	cache access mode (see #P0434)
 51h	cache timing/size control (see #P0435)
 52h	primary idle timer reloading control (see #P0436)
 53h	primary idle timer reload distinguish (see #P0437)
 54h	SMI triggering control (see #P0438)
 55h	SMI trigger distinguish (see #P0439)
 56h	clock frequency control (see #P0440)
 58h	general purpose timer (see #P0442)
 59h	timer control (see #P0443)
 5Ah	power/peripheral control (see #P0444)
 5Bh	system management control (see #P0445)
 5Eh	misc. cache control (see #P0448)
 5Fh	conserve mode/secondary idle timer control (see #P0449)
 60h	IRQ7-0 primary interrupt selection (see #P0450)
 61h	IRQ15-8 primary interrupt selection (see #P0451)
 63h	IRQ15-9 interrupt mode (see #P0453)
 64h	(see #P0454)
 65h	peripheral timer control (see #P0455)
 66h	(see #P0465)
 67h	peripheral timer (see #P0441)
 68h	multiple SMI triggering ???
 69h	multiple SMI triggering ???
 6Ah	multiple SMI triggering ???
 7Bh	general purpose input and output port ???
 7Ch	general purpose input and output port ???
 7Eh	general purpose output port ???
 7Fh	general purpose input and output port ???
 82h	PCI buffer control (see #P0466)
 83h	PCI data link control (see #P0467)
 84h	PCI interface timing (see #P0468)
 85h	PCI arbitration (see #P0469)
 86h	(see #P0470)
 93h	(see #P0471)
 9Ch	programmable chipselect A (see #P0472)
 9Dh	programmable chipselect A address mask (see #P0473)
 9Eh	programmable chipselect B (see #P0474)
 9Fh	programmable chipselect B address mask (see #P0475)
 FBh	plug and play DRQ routing (see #P0476)
 FCh	PCI interrupt polarity (see #P0477)
 FDh	plug and play IRQ routing (see #P0478)
 FEh	PCI IRQ routing 1 (see #P0479)
 FFh	PCI IRQ routing 2 (see #P0480)
SeeAlso: #P0419

Bitfields for Via VT82C570M DRAM type:
Bit(s)	Description	(Table P0462)
 7	Bank 3 DRAM type (used with bit 3)
	bits 7 and 3:
	00 = standard DRAM
	01 = burst EDO DRAM
	10 = EDO DRAM
	11 = illegal
 6	Bank 2 DRAM type (used with bit 2)
	bits 6 and 2: same values as for bits 7 and 3
 5	Bank 1 DRAM type (used with bit 1)
	bits 5 and 1: same values as for bits 7 and 3
 4	Bank 0 DRAM type (used with bit 0)
	bits 4 and 0: same values as for bits 7 and 3
 3	Bank 3 DRAM type (used with bit 7)
 2	Bank 2 DRAM type (used with bit 6)
 1	Bank 1 DRAM type (used with bit 5)
 0	Bank 0 DRAM type (used with bit 4)
SeeAlso: #P0461

Bitfields for Via VT82C570M register 48h:
Bit(s)	Description	(Table P0463)
 7	reserved
 6	eight CWE# pins for each byte in addition to global GWE# ???
 5-4	reserved
 3-0	DRAM operation width (if register 20h bit 0 = 1)
	0 = 64 bit operation for corresponding DRAM bank
	1 = 32 bit operation for corresponding DRAM bank
SeeAlso: #P0461

Bitfields for Via VT82C570M register 49h:
Bit(s)	Description	(Table P0464)
 5	0 = cache SRAM write enable for each bank
	1 = cache SRAM byte write enable
SeeAlso: #P0461

Bitfields for Via VT82C570M register 66h:
Bit(s)	Description	(Table P0465)
 3-2	peripheral timer (register 67h) time base
	00 = disable
	01 = 32.768 KHz
	10 = 1 sec
	11 = 1 min
SeeAlso: #P0461

Bitfields for Via VT82C570M PCI buffer control:
Bit(s)	Description	(Table P0466)
 7	CPU to PCI write buffer enable
 6	PCI to memory write buffer enable
 5	reserved
 4	PCI accessing memory prefetch buffer enable
 3	PCI accelerated decoding enable
 2	reserved
 1	on-board memory burst write enable
 0	on-board memory burst read enable
SeeAlso: #P0461

Bitfields for Via VT82C570M PCI data link control:
Bit(s)	Description	(Table P0467)
 7	data link write cycle
	0 = 1 wait state
	1 = 0 wait state
 6-4	reserved
 3	on-board memory detection point for PCI master
	0 = first address phase
	1 = first data phase
 2-1	reserved
 0	reserved (must be 0)
SeeAlso: #P0461

Bitfields for Via VT82C570M PCI interface timing:
Bit(s)	Description	(Table P0468)
 7	slave mode lock function enable
 6	retry count
	0 = 16 times
	1 = 64 times
 5	retry deadlock error reporting enable
 4	retry status occurred (write 1 to reset)
 3	CPU to PCI fast back to back enable
 2	fast FRAME# generation enable
 1-0	DEVSEL# decoding
	00 = fast
	01 = medium
	10 = slow
	11 = subtractive
SeeAlso: #P0461

Bitfields for Via VT82C570M PCI arbitration:
Bit(s)	Description	(Table P0469)
 7	0 = priority on PCI bus
	1 = fairness between CPU and PCI bus
 6	0 = REQ# based
	1 = FRAME# based
 5-4	CPU time slot in unit of
	00 = 4 PCI clocks
	01 = 8 PCI clocks
	10 = 16 PCI clocks
	11 = 32 PCI clocks
 3-0	PCI master bus time out
	0000 = disable
	0001-1111 = 1x32 - 15x32 PCI clocks
SeeAlso: #P0461

Bitfields for Via VT82C570M register 86h:
Bit(s)	Description	(Table P0470)
 7	PCI configuration mechanism #1/#2 (default #1)
SeeAlso: #P0461

Bitfields for Via VT82C570M register 93h:
Bit(s)	Description	(Table P0471)
 5	parity or system error at PCI bus signify
	0 = I/O channel check
	1 = NMI
SeeAlso: #P0461

Bitfields for Via VT82C570M programmable chipselect A:
Bit(s)	Description	(Table P0472)
 7-0	chipselect A address (high two bits in register 9Dh bits 1-0)
SeeAlso: #P0461,#P0473,#P0474

Bitfields for Via VT82C570M programmable chipselect A address mask:
Bit(s)	Description	(Table P0473)
 7-2	chipselect A address mask
 1-0	chipselect A address (low eight bits in register 9Dh)
SeeAlso: #P0461,#P0472,#P0474

Bitfields for Via VT82C570M programmable chipselect B:
Bit(s)	Description	(Table P0474)
 7-0	chipselect B address (high two bits in register 9Fh bits 1-0)
SeeAlso: #P0461,#P0472,#P0475

Bitfields for Via VT82C570M programmable chipselect B address mask:
Bit(s)	Description	(Table P0475)
 7-2	chipselect B address mask
 1-0	chipselect B address (low eight bits in register 9Eh)
SeeAlso: #P0461,#P0473,#P0474

Bitfields for Via VT82C570M plug and play DRQ routing:
Bit(s)	Description	(Table P0476)
 7-6	reserved
 5-3	PDRQ1 routing
	000-011 = DRQ0-3
	100 = reserved
	101-111 = DRQ5-7
 2-0	PDRQ0 routing
	000-011 = DRQ0-3
	100 = reserved
	101-111 = DRQ5-7
SeeAlso: #P0461

Bitfields for Via VT82C570M PCI interrupt polarity:
Bit(s)	Description	(Table P0477)
 7-4	reserved
 3	INTA# polarity (refer to note below)
 2	INTB# polarity
 1	INTC# polarity
 0	INTD# polarity
Note:	for bits 3-0, 0 = non-invert (level-sensitive), 1 = inverted (edge)
SeeAlso: #P0461

Bitfields for Via VT82C570M plug and play IRQ routing:
Bit(s)	Description	(Table P0478)
 7-4	INTD# routing (value indicates desired IRQ number; 0,2,13 are reserved)
 3-0	PIRQ0 routing (value indicates desired IRQ number; 0,2,13 are reserved)
SeeAlso: #P0461,#P0479,#P0480

Bitfields for Via VT82C570M PCI IRQ routing 1:
Bit(s)	Description	(Table P0479)
 7-4	INTA# routing (value indicates desired IRQ number; 0,2,13 are reserved)
 3-0	INTB# routing (value indicates desired IRQ number; 0,2,13 are reserved)
SeeAlso: #P0461,#P0478,#P0480

Bitfields for Via VT82C570M PCI IRQ routing 2:
Bit(s)	Description	(Table P0480)
 7-4	INTC# routing (value indicates desired IRQ number; 0,2,13 are reserved)
 3-0	PIRQ1 routing (value indicates desired IRQ number; 0,2,13 are reserved)
SeeAlso: #P0461,#P0478,#P0479

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P00A800A9 - PORT 00A8-00A9 - Via VT82C586A - GPIO

PORT 00A8-00A9 - Via VT82C586A - GPIO

00A8  ?W  configuration register index
00A9  RW  configuration register data

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P00B000BF - PORT 00B0-00BF - PC radio by CoZet Info Systems

PORT 00B0-00BF - PC radio by CoZet Info Systems
Range:	The I/O address range is dipswitch selectable from:
	   038-03F and 0B0-0BF
	   078-07F and 0F0-0FF
	   138-13F and 1B0-1BF
	   178-17F and 1F0-1FF
	   238-23F and 2B0-2BF
	   278-27F and 2F0-2FF
	   338-33F and 3B0-3BF
	   378-37F and 3F0-3FF
Notes:	All of these addresses show a readout of FFh in initial state.
	Once started, all of the addresses show	FBh, whatever might happen.

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P00B2 - PORT 00B2 - Intel chipsets - Advanced Power Management Control

PORT 00B2 - Intel chipsets - Advanced Power Management Control
Notes:	used to pass data between the operating system and the System
	  Management Interrupt (SMI) handler
	writes to this port can cause an SMI; reads can cause STPCLK# to be
	  asserted (putting the CPU in sleep mode)
	supported by 82420EX, 82371, and other Intel chipsets
SeeAlso: PORT 00B3h,#01079

00B2  RW  control

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P00B3 - PORT 00B3 - Intel chipsets - Advanced Power Management Status

PORT 00B3 - Intel chipsets - Advanced Power Management Status
Notes:	used to pass data between the operating system and the System
	  Management Interrupt (SMI) handler
	supported by 82420EX, 82371, and other Intel chipsets
SeeAlso: PORT 00B2h

00B3  RW  status

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P00C0 - PORT 00C0 - TI SN746496 programmable tone/noise generator (PCjr)

PORT 00C0 - TI SN746496 programmable tone/noise generator (PCjr)

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P00C000DF - PORT 00C0-00DF - DMA 2 - SECOND DIRECT MEMORY ACCESS CONTROLLER (8237)

PORT 00C0-00DF - DMA 2 - SECOND DIRECT MEMORY ACCESS CONTROLLER (8237)

00C0  RW  DMA channel 4 memory address bytes 1 and 0 (low) (ISA, EISA)
00C2  RW  DMA channel 4 transfer count bytes 1 and 0 (low) (ISA, EISA)
00C4  RW  DMA channel 5 memory address bytes 1 and 0 (low) (ISA, EISA)
00C6  RW  DMA channel 5 transfer count bytes 1 and 0 (low) (ISA, EISA)
00C8  RW  DMA channel 6 memory address bytes 1 and 0 (low) (ISA, EISA)
00CA  RW  DMA channel 6 transfer count bytes 1 and 0 (low) (ISA, EISA)
00CC  RW  DMA channel 7 memory address byte 0 (low), then 1 (ISA, EISA)
00CE  RW  DMA channel 7 transfer count byte 0 (low), then 1 (ISA, EISA)

00D0  R-  DMA channel 4-7 status register (ISA, EISA) (see #P0481)
00D0  -W  DMA channel 4-7 command register (ISA, EISA) (see #P0482)
00D2  -W  DMA channel 4-7 write request register (ISA, EISA)
00D4  -W  DMA channel 4-7 write single mask register (ISA, EISA) (see #P0484)
00D6  -W  DMA channel 4-7 mode register (ISA, EISA) (see #P0485)
00D8  -W  DMA channel 4-7 clear byte pointer flip-flop (ISA, EISA)

00DA  R-  DMA channel 4-7 read temporary register (ISA, EISA)
00DA  -W  DMA channel 4-7 master clear (ISA, EISA)
00DC  -W  DMA channel 4-7 clear mask register (ISA, EISA)
00DE  -W  DMA channel 4-7 write mask register (ISA, EISA) (see #P0486)
Notes:	the temporary register is used as holding register in memory-to-memory
	  DMA transfers; it holds the last transferred byte
	channel 4 is used for cascading the first (8-bit) DMA controller
	base/current address registers can only address the memory in 16-bit
	  words (i.e. they contain lines A1-A16 of the address bus with line
	  A0 always equal to 0); base/current word count registers contain the
	  number of 16-bit words
	command and request registers do not exist on PS/2 DMA controller

Bitfields for DMA channel 4-7 status register:
Bit(s)	Description	(Table P0481)
 7 = 1	channel 7 request
 6 = 1	channel 6 request
 5 = 1	channel 5 request
 4 = 1	channel 4 request
 3 = 1	terminal count on channel 7
 2 = 1	terminal count on channel 6
 1 = 1	terminal count on channel 5
 0 = 1	terminal count on channel 4
SeeAlso: #P0001,#P0482

Bitfields for DMA channel 4-7 command register:
Bit(s)	Description	(Table P0482)
 7	DACK sense active high
 6	DREQ sense active high
 5	=1  extended write selection
	=0  late write selection
 4	rotating priority instead of fixed priority
 3	compressed timing
 2	=1  enable controller
	=0  enable memory-to-memory transfer
 1-0	channel number (00 = 4 to 11 = 7)
SeeAlso: #P0002,#P0481,#P0484

Bitfields for DMA channel 4-7 request register:
Bit(s)	Description	(Table P0483)
 7-3	reserved (0)
 2	=0 clear request bit
	=1 set request bit
 1-0	channel number
	00 channel 4 select
	01 channel 5 select
	10 channel 6 select
	11 channel 7 select
SeeAlso: #P0003,#P0484

Bitfields for DMA channel 4-7 write single mask register:
Bit(s)	Description	(Table P0484)
 7-3	reserved
 2	=0  clear mask bit
	=1  set mask bit
 1-0	channel select
	00 channel 4 select
	01 channel 5 select
	10 channel 6 select
	11 channel 7 select
SeeAlso: #P0004,#P0482

Bitfields for DMA channel 4-7 mode register:
Bit(s)	Description	(Table P0485)
 7-6	transfer mode
	00  demand mode
	01  single mode
	10  block mode
	11  cascade mode
 5	direction
	0  address increment select
	1  address decrement select
 4	autoinitialisation enabled
 3-2	operation
	00  verify operation
	01  write to memory
	10  read from memory
	11  reserved
 1-0	channel number
	00  channel 4 select
	01  channel 5 select
	10  channel 6 select
	11  channel 7 select
SeeAlso: #P0005,#P0484

Bitfields for DMA channel 4-7 write mask register:
Bit(s)	Description	(Table P0486)
 7-4	reserved
 3	channel 7 mask bit
 2	channel 6 mask bit
 1	channel 5 mask bit
 0	channel 4 mask bit
Note:	each mask bit is automatically set when the corresponding channel
	  reaches terminal count or an extenal EOP sigmal is received
SeeAlso: #P0484,#P0006

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P00E000E1 - PORT 00E0-00E1 - CHIPSET FROM ACT

PORT 00E0-00E1 - CHIPSET FROM ACT

00E0  ?W  index for accesses to data port
00E1  R?  chip set data

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P00E000E7 - PORT 00E0-00E7 - MICROCHANNEL

PORT 00E0-00E7 - MICROCHANNEL

00E0  RW  split address register, memory encoding registers PS/2m80 only
	(see #P0487)
00E1  RW  memory register (see #P0488,#P0489)
00E3  RW  error trace (bits 23-16 of address on last rising edge of ERS line)
00E4  RW  error trace (bits 15-8 of address on last rising edge of ERS line)
00E5  RW  error trace (see #P0490)
00E7  RW  error trace (see #P0491)

Bitfields for Microchannel Split Address Register:
Bit(s)	Description	(Table P0487)
 7-6	unused
 5-4	2MB memory for connector 2 on Type2 motherboard
	bit 5: second MB disabled or not present
	bit 4: first MB disabled or not present
 3-0	address at which to place leftover from split in first MB, in MB
	(1-15, 0 is invalid when split is active)
SeeAlso: #P0488,#P0489

Bitfields for Microchanel Memory Register, Type1 motherboard:
Bit(s)	Description	(Table P0488)
 7-6	1 MB memory for connector 2
	10 installed
	11 not installed
 5-4	1 MB memory for connector 1
	10 installed
	11 not installed
 3-1	split memory select
		ROM   convmem	over1M
	001	ON	640K	384K
	011	ON	512K	512K
	100	shadow	640K	0K
	101	ON	640K	0K
	110	shadow	512K	0K
	111	ON	512K	0K
 0	parity checking
	=0 enable
	=1 clear parity error (write 0 to re-enable parity checking)
SeeAlso: #P0487,#P0489

Bitfields for Microchannel Memory Register, Type2 motherboard:
Bit(s)	Description	(Table P0489)
 7-6	unused
 5-4	memory connector 1
	bit 5: second MB disabled or not present
	bit 4: first MB disabled or not present
 3-1	split memory select
		ROM   convmem	over1M
	000	shadow	640K	256K
	001	ON	640K	384K
	010	shadow	512K	384K
	011	ON	512K	512K
	100	shadow	640K	0K
	101	ON	640K	0K
	110	shadow	512K	0K
	111	ON	512K	0K
 0	parity checking
	=0 enable
	=1 clear parity error (write 0 to re-enable parity checking)
SeeAlso: #P0487,#P0488

Bitfields for Microchannel Error Trace register E5h:
Bit(s)	Description	(Table P0490)
 7-2	bits 7-2 of address on last rising edge of ERS line
 1	address space (0=I/O, 1=memory)
 0	=1 bus-master arbitration cycle
SeeAlso: #P0491

Bitfields for Microchannel Error Trace register E7h:
Bit(s)	Description	(Table P0491)
 7-1	unused
 0	bus cycle type
	=0 control (instruction fetch, halt, interrupt acknowledge)
	=1 data
SeeAlso: #P0490

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P00E000EF - PORT 00E0-00EF - IBM PS/1 CLOCK

PORT 00E0-00EF - IBM PS/1 CLOCK

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P00E1 - PORT 00E1 - STB PowerMEG - ???

PORT 00E1 - STB PowerMEG - ???
Desc:	the STB PowerMEG is a memory expansion card capable of providing EMS

00E1  RW  ???
	  bit 0: ???

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P00E2 - PORT 00E2 - S3 Trio64V+ - I2C PORT

PORT 00E2 - S3 Trio64V+ - I2C PORT
Range:	PORT 00E2h or PORT 00E8h; default depends on external pin, but can
	  be reprogrammed via chip's CR6F
SeeAlso: PORT 00E8h,#M0079

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P00E8 - PORT 00E8 - S3 Trio64V+ - I2C PORT

PORT 00E8 - S3 Trio64V+ - I2C PORT
Range:	PORT 00E2h or PORT 00E8h; default depends on external pin, but can
	  be reprogrammed via chip's CR6F
SeeAlso: PORT 00E2h,#M0079

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P00EB - PORT 00EB - Intel "Triton" chipset - ???

PORT 00EB - Intel "Triton" chipset - ???
SeeAlso: PORT 0085h"Triton"

00EB  ?W  ???

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P00EB - PORT 00EB - DUMMY PORT FOR DELAY???

PORT 00EB - DUMMY PORT FOR DELAY???
Note:	on a number of machines, the BIOS appears to write a copy of any
	  data sent to numerous other ports to this port as well; it seems
	  to be a dummy port used for short delays between writes to other
	  ports (used instead of JMP $+2, which no longer delays on Pentium+)
SeeAlso: PORT 00ED"DUMMY"

00EB  ?W  ???

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P00EC00ED - PORT 00EC-00ED - Compaq LTE Elite

PORT 00EC-00ED - Compaq LTE Elite

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P00ED - PORT 00ED - DUMMY PORT FOR DELAY???

PORT 00ED - DUMMY PORT FOR DELAY???
Note:	on a number of machines, the BIOS appears to write a copy of any
	  data sent to numerous other ports to this port as well; it seems
	  to be a dummy port used for short delays between writes to other
	  ports (used instead of JMP $+2, which no longer delays on Pentium+)
SeeAlso: PORT 00EB"DUMMY"

00EDw  ?W  ???

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P00EF - PORT 00EF - Hyunday Super-NB386S (AMD386sx with Intel chipset)

PORT 00EF - Hyunday Super-NB386S (AMD386sx with Intel chipset)
Warning: any access to this port causes a cold reset on this machine!

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P00F000F5 - PORT 00F0-00F5 - PCjr Disk Controller

PORT 00F0-00F5 - PCjr Disk Controller

00F0  ??  disk controller
00F2  ??  disk controller control port
00F4  ??  disk controller status register
00F5  ??  disk controller data port

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P00F000FF - PORT 00F0-00FF - MATH COPROCESSOR (8087..80387)

PORT 00F0-00FF - MATH COPROCESSOR (8087..80387)

00F0  -W  math coprocessor clear busy latch (write 00h)
00F1  -W  math coprocessor reset (write 00h)
00F8  RW  opcode transfer (CPU-coprocessor communication)
00FA  RW  opcode transfer
00FC  RW  opcode transfer

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P00F9 - PORT 00F9 - Compaq LTE Elite

PORT 00F9 - Compaq LTE Elite

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P00FB - PORT 00FB - Compaq LTE Elite

PORT 00FB - Compaq LTE Elite

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P00F900FF - PORT 00F9-00FF - PC radio by CoZet Info Systems

PORT 00F9-00FF - PC radio by CoZet Info Systems
Range:	The I/O address range is dipswitch selectable from:
	   038-03F and 0B0-0BF
	   078-07F and 0F0-0FF
	   138-13F and 1B0-1BF
	   178-17F and 1F0-1FF
	   238-23F and 2B0-2BF
	   278-27F and 2F0-2FF
	   338-33F and 3B0-3BF
	   378-37F and 3F0-3FF
Notes:	All of these addresses show a readout of FFh in initial state.
	Once started, all of the addresses show	FBh, whatever might happen.

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P0100 - PORT 0100 - 3COM 3C509 Ethernet card - ID port

PORT 0100 - 3COM 3C509 Ethernet card - ID port
Note: this port is present only on the 3C509, not on any other 3COM card
SeeAlso: PORT 0110h,PORT 0120h

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P01000107 - PORT 0100-0107 - PS/2 POS (Programmable Option Select)

PORT 0100-0107 - PS/2 POS (Programmable Option Select)
Note:	the default value for PORT 0102h is stored in CMOS 31h

0100  R	  POS register 0	Low adapter ID byte
0101  R	  POS register 1	High adapter ID byte
0102  RW  POS register 2	option select data byte 1 (see #P0492)
0103  RW  POS register 3	option select data byte 2 (see #P0493)
0104  RW  POS register 4	option select data byte 3
0105  RW  POS register 5	option select data byte 4
		 bit 7	channel active (-CHCK)
		 bit 6	channel status
0106  RW  POS register 6	Low subaddress extension
0107  RW  POS register 7	High subaddress extension

Bitfields for PS/2 POS register 2, option select data byte 1:
Bit(s)	Description	(Table P0492)
 7	  0  = unidirectional LPT port
	  1  = bidirectional LPT port
 6-5	PS/2 Model 50 and higher
	 00b = default LPT port at 3BCh
	 01b = ""		   378h
	 10b = ""		   278h
	 11b = reserved
 4	enable parallel port
 3	serial port address
	=0 COM2 (02F8h, IRQ3)
	=1 COM1 (03F8h, IRQ4)
 2	enable serial port
 1	enable diskette controller
 0	(MCA) =0 override bits 1,2,4 and disable devices
 0	card enable (CDEN)
 0	=1 VGA sleep bit, disconnects output drivers from VGA (usage for VGA
	  without monitor)
---ET4000---
 7-4	reserved???
 3	video RAM wait enable
 2	ET4000: ROM BIOS wait enable
 1	ET4000: I/O wait enable
Note:	access to this port is only possible when PORT 0094h bit 7 is low.
SeeAlso: #P0493

Bitfields for Chips&Technologies 64200 "Wingine" setup register:
Bit(s)	Description	(Table P0493)
 7	enable access to extended registers (see #P0762)
Note:	on some C&T graphics chips, this register can be made read-only
	  via XR70 (see #P0762)
SeeAlso: #P0492

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P0100010F - PORT 0100-010F - CompaQ Tape drive adapter. alternate address at 0300

PORT 0100-010F - CompaQ Tape drive adapter. alternate address at 0300

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P0102 - PORT 0102 - Chips & Technologies 64310 - GLOBAL ENABLE REGISTER

PORT 0102 - Chips & Technologies 64310 - GLOBAL ENABLE REGISTER
SeeAlso: PORT 0106"Chips"

0102  RW  global enable register (see #P0494)

Bitfields for Chips & Technologies 64310 global enable register:
Bit(s)	Description	(Table P0494)
 7-1	reserved (0)
 0	VGA sleep (used if port 102h bit 1 = 0)
	0 = VGA disabled
	1 = VGA enabled
Note:	Only accessible in setup mode (port 46E8h bit 4 = 1).
SeeAlso: #P0495,#P0492

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P0106 - PORT 0106 - Chips & Technologies 64310 - MOTHERBOARD DISABLE REGISTER

PORT 0106 - Chips & Technologies 64310 - MOTHERBOARD DISABLE REGISTER
SeeAlso: PORT 0102"Chips"

0106  RW  motherboard disable register (see #P0495)

Bitfields for Chips & Technologies 64310 motherboard disable register:
Bit(s)	Description	(Table P0495)
 7-2	reserved (0)
 1	sleep control
	0 = port 102h bit 0 controls VGA sleep (default)
	1 = port 106h bit 0 controls VGA sleep
 0	VGA sleep (used if bit 1 = 1)
	0 = VGA disabled
	1 = VGA enabled
Note:	Only accessible in setup mode (port 46E8h bit 4 = 1),
	  if XR01 bit 2 = 1.
SeeAlso: #P0494

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P0108010F - PORT 0108-010F - IBM PS/2 - 8 digit LED info panel

PORT 0108-010F - IBM PS/2 - 8 digit LED info panel

010F  -W  leftmost character on display
010E  -W  second character
 ...
0108  -W  eighth character

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P0110 - PORT 0110 - 3COM 3C509 Ethernet card - ID port (alternate address)

PORT 0110 - 3COM 3C509 Ethernet card - ID port (alternate address)
Note:	this port is present only on the 3C509, not on any other 3COM card
SeeAlso: PORT 0100h"3COM",PORT 0120h"3COM"

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P0120 - PORT 0120 - 3COM 3C509 Ethernet card - ID port (alternate address)

PORT 0120 - 3COM 3C509 Ethernet card - ID port (alternate address)
Note:	this port is present only on the 3C509, not on any other 3COM card
SeeAlso: PORT 0100h"3COM",PORT 0110h"3COM"

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P0130013F - PORT 0130-013F - CompaQ SCSI adapter. alternate address at 0330

PORT 0130-013F - CompaQ SCSI adapter. alternate address at 0330

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P01300133 - PORT 0130-0133 - Adaptec 154xB/154xC SCSI adapter

PORT 0130-0133 - Adaptec 154xB/154xC SCSI adapter
Range:	four ports at any of 0130, 0134, 0230, 0234, 0330 (default) or 0334

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P01340137 - PORT 0134-0137 - Adaptec 154xB/154xC SCSI adapter

PORT 0134-0137 - Adaptec 154xB/154xC SCSI adapter
Range:	four ports at any of 0130, 0134, 0230, 0234, 0330 (default) or 0334

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P0138013F - PORT 0138-013F - PC radio by CoZet Info Systems

PORT 0138-013F - PC radio by CoZet Info Systems
Range:	The I/O address range is dipswitch selectable from:
	   038-03F and 0B0-0BF
	   078-07F and 0F0-0FF
	   138-13F and 1B0-1BF
	   178-17F and 1F0-1FF
	   238-23F and 2B0-2BF
	   278-27F and 2F0-2FF
	   338-33F and 3B0-3BF
	   378-37F and 3F0-3FF
Notes:	All of these addresses show a readout of FFh in initial state.
	Once started, all of the addresses show	FBh, whatever might happen.

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