Index for category C - CPU-generated

Table of Contents by Order
00 - INT 00 C - CPU-generated - DIVIDE ERROR
01 - INT 01 C - CPU-generated - SINGLE STEP
01 - INT 01 C - CPU-generated (80386+) - DEBUGGING EXCEPTIONS
03 - INT 03 C - CPU-generated - BREAKPOINT
04 - INT 04 C - CPU-generated - INTO DETECTED OVERFLOW
05 - INT 05 C - CPU-generated (80186+) - BOUND RANGE EXCEEDED
06 - INT 06 C - CPU-generated (80186+) - INVALID OPCODE
07 - INT 07 C - CPU-generated (80286+) - PROCESSOR EXTENSION NOT AVAILABLE
08 - INT 08 C - CPU-generated (80286+) - DOUBLE EXCEPTION DETECTED
09 - INT 09 C - CPU-generated (80286,80386) - PROCESSOR EXTENSION PROTECTION ERROR
0A - INT 0A CP - CPU-generated (80286+) - INVALID TASK STATE SEGMENT
0B - INT 0B CP - CPU-generated (80286+) - SEGMENT NOT PRESENT
0C - INT 0C C - CPU-generated (80286+) - STACK FAULT
0D - INT 0D C - CPU-generated (80286+) - GENERAL PROTECTION VIOLATION
0E - INT 0E C - CPU-generated (80386+ native mode) - PAGE FAULT
10 - INT 10 C - CPU-generated (80286+) - COPROCESSOR ERROR
11 - INT 11 - CPU-generated (80486+) - ALIGNMENT CHECK
12 - INT 12 - CPU-generated (Pentium +) - MACHINE CHECK EXCEPTION

INT 00 C - CPU-generated - DIVIDE ERROR
Desc:	generated if the divisor of a DIV or IDIV instruction is zero or the
	  quotient overflows the result register; DX and AX will be unchanged.
Notes:	on an 8086/8088, the return address points to the following instruction
	on an 80286+, the return address points to the divide instruction
	an 8086/8088 will generate this interrupt if the result of a division
	  is 80h (byte) or 8000h (word)
SeeAlso: INT 04,OPCODE "AAD"

INT 01 C - CPU-generated - SINGLE STEP
Desc:	generated after each instruction if TF (trap flag) is set; TF is
	  cleared on invoking the single-step interrupt handler
Notes:	interrupts are prioritized such that external interrupts are invoked
	  after the INT 01 pushes CS:IP/FLAGS and clears TF, but before the
	  first instruction of the handler executes
	used by debuggers for single-instruction execution tracing, such as
	  MS-DOS DEBUG's T command
SeeAlso: INT 03"CPU"

INT 01 C - CPU-generated (80386+) - DEBUGGING EXCEPTIONS
Desc:	generated by the CPU on various occurrences which may be of interest
	  to a debugger program
Note:	events which may trigger the interrupt:
	  Instruction address breakpoint fault - will return to execute inst
	  Data address breakpoint trap - will return to following instruction
	  General detect fault, debug registers in use
	  Task-switch breakpoint trap
	  undocumented 386/486 opcode F1h - will return to following instruc
SeeAlso: INT 03"CPU"

INT 03 C - CPU-generated - BREAKPOINT
Desc:	generated by the one-byte breakpoint instruction (opcode CCh)
Notes:	used by debuggers to implement breakpoints, such as MS-DOS DEBUG's G
	  command
	also used by Turbo Pascal versions 1,2,3 when {$U+} specified
	return address points to byte following the breakpoint instruction
	called by Novell DOS 7 EMM386 after displaying an exception error
	  message (GPF, illegal opcodes, etc.) and before waiting for user
	  input
	called by QEMM-386 if the user presses 'I' (undocumented) when prompted
	  after an exception error message
SeeAlso: INT 01"CPU"

INT 04 C - CPU-generated - INTO DETECTED OVERFLOW
Desc:	the INTO instruction will generate this interrupt if OF (Overflow Flag)
	  is set; otherwise, INTO is effectively a NOP
Note:	may be used for convenient overflow testing (to prevent errors from
	  propagating) instead of JO or a JNO/JMP combination
SeeAlso: INT 00"CPU",OPCODE "AAD",OPCODE "AAM"

INT 05 C - CPU-generated (80186+) - BOUND RANGE EXCEEDED
Desc:	generated by BOUND instruction when the value to be tested is less than
	  the indicated lower bound or greater than the indicated upper bound.
Note:	returning from this interrupt re-executes the failing BOUND instruction

INT 06 C - CPU-generated (80186+) - INVALID OPCODE
Desc:	this interrupt is generated when the CPU attempts to execute an
	  invalid opcode (most protected-mode instructions are considered
	  invalid in real mode) or a BOUND, LDS, LES, or LIDT instruction
	  which specifies a register rather than a memory address
Notes:	return address points to beginning of invalid instruction
	with proper programming, this interrupt may be used to emulate
	  instructions which do not exist; many 386 BIOSes emulate the 80286
	  undocumented LOADALL instruction which was removed from the 80386+
	generated by the 80386+ when the LOCK prefix is used with instructions
	  other than BTS, BTR, BTC, XCHG, XADD (486), CMPXCHG (486), INC, DEC,
	  NOT, NEG, ADD, ADC, SUB, SBB, AND, OR, or XOR, or any instruction
	  not accessing memory.
SeeAlso: INT 0C"CPU",INT 0D"CPU"

INT 07 C - CPU-generated (80286+) - PROCESSOR EXTENSION NOT AVAILABLE
Desc:	this interrupt is automatically called if a coprocessor instruction is
	  encountered when no coprocessor is installed
Note:	can be used to emulate a numeric coprocessor in software
SeeAlso: INT 09"CPU"

INT 08 C - CPU-generated (80286+) - DOUBLE EXCEPTION DETECTED
Desc:	called when multiple exceptions occur on one instruction, or an
	  exception occurs in an exception handler
Notes:	called in protected mode if an interrupt above the defined limit of
	  the interrupt vector table occurs
	return address points at beginning of instruction with errors or the
	  beginning of the instruction which was about to execute when the
	  external interrupt caused the exception
	if an exception occurs in the double fault handler, the CPU goes into
	  SHUTDOWN mode (which circuitry in the PC/AT converts to a reset);
	  this "triple fault" is a faster way of returning to real mode on
	  many 80286 machines than the standard keyboard controller reset

INT 09 C - CPU-generated (80286,80386) - PROCESSOR EXTENSION PROTECTION ERROR
Desc:	called if the coprocessor attempts to access memory outside a segment
	  boundary; it may occur at an arbitrary time after the coprocessor
	  instruction was issued
Notes:	until the condition is cleared or the coprocessor is reset, the only
	  coprocessor instruction which may be used is FNINIT; WAIT or other
	  coprocessor instructions will cause a deadlock because the
	  coprocessor is still busy waiting for data
	for the 486+, a coprocessor protection error generates an INT 0D
SeeAlso: INT 07"CPU"

INT 0A CP - CPU-generated (80286+) - INVALID TASK STATE SEGMENT
Desc:	automatically called during a task switch if the new TSS specified by
	  the task gate is invalid for any of the following reasons:
		TSS limit is less than 43 (80286) or 103 (80386/80486)
		LDT selector invalid or segment not present
		null SS selector, or SS selector outside LDT/GDT limit
		stack segment is read-only
		stack segment DPL differs from new CPL, or RPL <> CPL
		CS selector is outside LDT/GDT limit or not code
		non-conforming code segment's DPL differs from CPL
		conforming code segment's DPL > CPL
		DS/ES selectors outside LDT/GDT limit or not readable segments
Note:	the handler must use a task gate in order to have a valid TSS under
	  which to execute; it must also reset the busy bit in the new TSS
SeeAlso: INT 0B"CPU"

INT 0B CP - CPU-generated (80286+) - SEGMENT NOT PRESENT
Desc:	generated when loading a segment register if the segment descriptor
	  indicates that the segment is not currently in memory, unless the
	  segment is an LDT (see INT 0A"CPU") or stack segment (see
	  INT 0C"CPU") needed by a task switch
Note:	may be used to implement virtual memory by loading in segments as they
	  are accessed, clearing the "not present" bit after loading
SeeAlso: INT 0A"CPU",INT 0E"CPU"

INT 0C C - CPU-generated (80286+) - STACK FAULT
Desc:	this interrupt is generated in protected mode on a stack overflow or
	  underflow, or if an inter-level transition or task switch references
	  a stack segment marked "not present"; it is generated in real mode
	  on accessing a word operand at SS:FFFFh
Note:	the 80286 will shut down in real mode if SP=1 before a push.  On the
	  PC AT and compatibles, external circuitry generates a reset on
	  shutdown.
SeeAlso: INT 0B"CPU",INT 0D"CPU"

INT 0D C - CPU-generated (80286+) - GENERAL PROTECTION VIOLATION
Desc:	the CPU generates this interrupt when it detects a protection violation
	  which does not fit under any other category having a separate
	  interrupt
Notes:	called in real mode when
	    an instruction accesses a memory operand extending beyond offset
	      FFFFh (i.e. WORD at FFFFh or DWORD at FFFDh or higher) in segment
	      CS, DS, ES, FG, or GS
	    a PUSH MEM or POP MEM instruction contains an invalid bit encoding
	      in the second byte
	    an instruction exceeds the maximum length allowed (10 bytes for
	      80286, 15 bytes for 80386/80486)
	    an instruction wraps from offset FFFFh to offset 0000h
	called in protected mode on protection violations not covered by INT 06
	  through INT 0C, including
	    segment limit violations
	    write to read-only segments
	    accesses using null DS or ES selectors
	    accesses to segments with privilege greater than CPL
	    wrong descriptor type
	called on 80486 protected-mode floating-point protection fault
SeeAlso: INT 09"80486",INT 0C"STACK"

INT 0E C - CPU-generated (80386+ native mode) - PAGE FAULT
Desc:	this interrupt is generated in protected and virtual-86 modes on
	  attempting to access a 4K memory page whose page table entry has
	  the "present" bit cleared
Notes:	used to implement virtual memory--when the page fault occurs, the
	  operating system can load the appropriate page from disk
	a protected-mode program written in the Flat memory model will often
	  generate this interrupt (typically reported as an Exception #14 or
	  Exception 0E with a register dump) when dereferencing an
	  uninitialized or corrupted pointer
SeeAlso: INT 0B"CPU"

INT 10 C - CPU-generated (80286+) - COPROCESSOR ERROR
Desc:	this interrupt is generated by the CPU when the -ERROR pin is asserted
	  by the coprocessor
Note:	AT's and clones usually wire the coprocessor to use IRQ13, but not all
	  get it right
SeeAlso: INT 09"hardware",INT 75

INT 11 - CPU-generated (80486+) - ALIGNMENT CHECK
Desc:	automatically generated by the CPU when the AC flag is set, the current
	  privilege level is 3, and a misaligned memory access (WORD not on an
	  even address or DWORD not on a multiple of 4) is made
Note:	not all V86 monitors allow the AC flag to be set, such as Turbo
	  Debugger 386
SeeAlso: INT 12"CPU"

INT 12 - CPU-generated (Pentium +) - MACHINE CHECK EXCEPTION
Notes:	Intel documents this interrupt as CPU model-dependent
	for current Pentium processors, the reason for the machine check
	  exception may be read from model-specific registers 00h and 01h
	  (described, for example, in Christian Ludloff's 4P package)
	for Pentium Pro/II processors,	the reason may be read from the
	  MCG_STATUS MSR (see MSR 0000017Ah)
	this exception is enabled by bit 6 of CR4
SeeAlso: INT 11"CPU",MSR 00000000h,MSR 00000001h,MSR 0000017Ah